This PDF file contains the front matter associated with SPIE Proceedings Volume 11177, including the Title Page, Copyright information, Table of Contents, Author and Conference Committee lists.

Lithographers are currently unable to generate quality patterning at tight pitches with values of k1 that are as low as have been achieved routinely using ArF immersion patterning, a situation that is largely due to the continuing pursuit of resists with low exposure doses. As a consequence, multiple patterning may be required to scale to a second node with EUV lithography, which reduces its cost-effectiveness, even if each individual exposure is done with a low exposure dose. Because of process control limitations, such multiple patterning may necessarily be triple or quadruple patterning, rather than double patterning. Processes with reduced line-edge roughness (LER) could be applied to front-end layers, increasing the value of EUV lithography. High-NA EUV lithography is in development, with a number of technical issues requiring solution, but with no apparent show-stoppers.

This paper shows the latest challenges facing mask blank evolution to support leading-edge lithography processes. ArF immersion lithography has been employing multi-pass exposures to exceed the physical diffraction limit. These photomasks demand very accurate overlay, higher NILS and best CD uniformity for wider process window. The subject was considered from two perspectives from a mask blank producer, which are the mask-making perspective and the wafer lithography perspective. To improve the overlay, we introduced the dedicated CDL (Charge Dissipation Layer) for improving mask registration error. From the lithography resolution perspective, we have developed a high-transmittance phase-shifter film for higher NILS. CDU stability point of view, we described “Superior pattern fidelity CAR”, “High ArF durability SiN phase-shifter” and “Transparent etching stopper”. The industry decided to move to EUV lithography. But there are still many challenges for optical lithography.

The benefit of complex and curvilinear mask shapes as well as the demand for fast mask production cycles has been driving the development of Multi-Beam Mask Writers (MBMW) for several years. Meanwhile, those writers have reached a quality level where they can be integrated into mask production flows at various nodes and even be used for writing imprint lithography templates at wafer scale. 50 keV e-beam writers whether Multi-Beam or Variable Shaped Beam (VSB), are affected by scattering effects at various length scales and require significant corrections in order to print mask features on target. Correction methods for long-range effects such as PEC (Proximity Effect Correction) and FEC (Fogging Effect Correction) have been developed for VSB machines and can be applied to MBMWs in the same way. Similarly, long-range mask process effects like loading (LEC) can be corrected using the same methods as developed for VSB machines. Besides long-range scattering and etch effects, critical masks for the 14 nm technology node and below are affected by short-range scattering and etch effects like e-beam forward scattering and etch micro-loading. Those effects increase at length scales below several 100 nm and change printed CDs significantly at minimum feature sizes on DUV and EUV masks where SRAFs are targeted around 60 nm and 30 nm, respectively. Figure 1 (left) shows an example of a typical mask CD error signature where the range of CD errors from small, isolated features to large nested features can easily cover 15 nm or more. Those short range distortions are generally corrected using so called Mask-Process-Correction (MPC) tools which compensate mask errors by moving edges of the input design and optionally adjust the dose of printed features locally. Simulated mask contours before and after MPC are shown in Figure 1 (center, right) demonstrating the large effect of MPC on SRAFs but also the non-negligible effect on main feature CDs, especially on line-ends and narrow lines.

The currently increasing demand for photo-masks in the regime of the 14nm technology drives many initiatives towards capacity and throughput increase of existing production line. Such improvements are facilitated by improved control mechanisms of the tools and processes used within a production line. While process control of long range parameters such as the average CD behavior is demanding yet conceptually well understood, other parameters such as the small scales CD properties are quite often elusive to process control. These properties often require a dedicated test mask to be processed in order to be validated. In this paper we introduce a systematic approach towards a product based monitoring of small scale CD behavior which uses a CD characteristic extracted from the defect inspection process. This characteristic represents the influence of CD relevant processes starting from 200m up to 4000 m. Large variations in the scale and magnitude of the CD characteristic are induced by layout specific design variations. However, the shape of these distinct curves is remarkably similar, which enables their use for monitoring as well as controlling the mask processes on the above stated spatial scales. In this paper it is demonstrated, that a meaningful process evaluation can be performed by using the classification capabilities of the support vector machines. The small scales CD characteristics presented in figure 1 originate from two distinct tools. Matching of the two tools can be assessed by training a support vector machine to classify the small scales CD characteristics according to their origin. The classification performance on the resampled training set as well as on the validation set is a robust measure for tool matching. The results of this approach are depicted in figure 2. The left panel shows the AUC statistics of bootstrapping resamples for tool comparison “A”. In this case no noticeable difference between the two tools is found (an average AUC of 0.55 suggest no learnable difference). This is contrasted by the tool comparison “B”, here the classifier has an average AUC of 0.75, indicating a learnable difference in the tool performances. This result is backed by the process understand of both tool types.

As it has been widely announced by the leading foundries, and confirmed by ASML, EUV Lithography is being introduced into high volume manufacturing (HVM) since the beginning of this year, in order to enable a more cost-effective manufacturing for the 7nm logic technology node. Very soon, the next technology node will be introduced and the number of EUV layers at 5nm is expected to increase significantly. Although EUV masks are not regarded as the first critical issue for EUV introduction into HVM, several items with respect to EUV masks need more time for improvements, certainly for 5nm and beyond. This presentation will address several mask related items such as EUV pellicle, alternative absorber, EUV mask lifetime, etc... and finally anamorphic masks. This paper is reviewing the status and outlook for these remaining challenges.

EUV technology with its state-of-the-art tool generation equipped with a Numerical Aperture (NA) of 0.33 and providing 13 nm resolution is on the brink of entering high volume manufacturing. Extending the roadmap down to a resolution of 8 nm requires a high-NA successor tool. ASML and ZEISS are jointly developing an EUV scanner system with an NA of 0.55 to enable the continuation of Moore’s law throughout the next decade. In this paper we motivate the top-level requirements of this high-NA tool, deduce implications on system design and present how they are solved in the tool. In particular, we address implications of the high-NA leading to large mirror sizes, introduction of a central obscuration and an anamorphic lens design resulting in the transition from full to half field. A consequence of the high-NA is a reduced depth of focus which is dealt with by an improved focus control of the system. The aberration level of the high-NA tool will be significantly reduced w.r.t. the NA 0.33 tool generation. This is achieved by extreme aspheres accompanied by an advanced mirror manufacturing process with corrections down to atomic scale. To enable mirror manufacturing to this precision the limits of mirror metrology are pushed out by transferring the whole measurement process into vacuum. Finally, we will give an update on the current status of the high-NA tool development and the build-up of the necessary infrastructure.

Pattern defects and uninvited particles (residuals) probably appear on Mask and Wafer in any manufacturing process of integrated circuits (ICs) and impact the final yield of IC chips. To ensure a high yield, defect inspection of Mask and Wafer has been broadly adopted for monitoring many processes in high volume manufacturing (HVM) and shortening development cycle-times of critical processes in R&D. In HVM optical inspection tools have played a major role, and in R&D e-beam inspection tools have been a critical role. For the 7nm technology node and beyond, minimum size killer defects are going to be invisible for optical inspection tools, and e-beam inspection tools are too slow to capture smaller killer defects in an acceptable throughput. Accordingly, enhancing e-beam inspection tools in throughput has become an issue demanding prompt attention, and one promising solution is multi-beam inspection (MBI) technology. We are developing a MBI tool, which combines our cutting edge technologies in multi-beam electron optics, sample stage, scanning strategy and computational architecture. In this paper we will introduce MBI technology and development progress of our MBI tool, and will discuss future application of MBI technology.

In this work we address the capability of an alternative overlay evaluation method for the entire BEOL-Process of IHP’s standard 0.25 and 0.13 μm SiGe:C BiCMOS technology. A dual lithography platform NIKON® NSR 210D/207D scanners and NIKON® NSR SF-150 i-Line stepper layer crossing and wafer bow related overlay issues will be discussed. Stack alignment marks, which serves the exposure alignment and overlay determination were introduced. A mismatch for overlay (x/y) |mean| + 3σ values below 8 nm between the KLA® ARCHER 100 overlay and both lithography tools could be demonstrated.

The continuation of Moore’s law demands the continuous development of EUV lithography. After the NXE:3400B scanner, currently being inserted in high-volume manufacturing (HVM), the next logical step is to increase the numerical aperture (NA) of the EUV projection optics, from 0.33 to 0.55, resulting in a high-NA EUV scanner. Looking back at the history of lithography tools developed in the last decades, we can see that such an increase of NA is, in relative terms, unprecedented (0.55 = 0.33 + 67%). This significant step forward in the NA is a challenge on many fronts and requires many adaptations. In this paper you will find an overview of the key concepts that make high-NA lithography different on imaging end, how the imaging assures the continued life of Moore’s law for the years to come and what are potential mask-related developments that would contribute to high-NA’s success.

The introduction of advanced technology nodes in deep UV (DUV) lithography (litho), involving multiple litho steps, has tightened the wafer on-product overlay specifications [1]. The industry trend already pushes the overlay requirements to the sub-nanometer regime (and so the mask registration requirements tightens as well). In the most general view, wafer on-product overlay errors are a combination of intra-field (within field) and inter-field (field-to-field) errors. A given litho layer intra-field overlay error includes several systematic sources, such as scanner lens-to-lens residuals and mask writer residuals. Parallel to the nodes and litho techniques advancing, the ability to accurately measure overlay at high lateral resolution have being successfully introduced, both at wafer and mask side. The recent developments in scanner technology improved the ability to control intra-field overlay at high-order across the exposure field. However, this is still in several millimeter lateral resolution control ability at its best, leaving residual errors in the sub-millimeter to few millimeter regime without the ability to further suppress them to the target specification, nevertheless, not to the sub-nanometer magnitude. In this work, we have empirically evaluated the ZEISS state-of-the-art mask tuning solution named ForTune ERC (Enhanced Registration Control). This solution is based on laser processing of the mask bulk by the ZEISS ForTune tool. It allows to suppress few nanometer overlay residuals (post the scanner best-can-do) down to deep sub-nanometer, all even at sub-millimeter sampling resolution (x1 wafer level) and low-to-high residuals modulating frequency. For the sake of this study, we have used a dual-image mask to form one overlay signature at wafer side. Two wafers have been exposed prior to the laser-based tuning of the mask bulk; the wafers overlay error was measured and used as an initial overlay problem to begin with. A second exposure of two additional wafers was performed post the problem- solving by the ERC model and the consequent mask laser-based tuning. The pre/post wafers were then compared to examine the improvement in overlay at wafer side. CD uniformity (CDU) data has been collected as well, to confirm no degradation in CDU due to the ForTune ERC process. The combination of this advanced method of intra-field control with high-order correction per exposure (CPE) by the scanner, provides an efficient co-optimized solution to tightly control the overlay of existing and future nodes at DUV litho.

In this work, we describe an effective and simple method for surface patterning of 3D objects with antireflective moth-eye structures via UV based nanoimprint lithography using soft stamps. So-called anti-reflective moth-eye structures are subwavelength nanostructures that can reduce the reflection of surfaces over the entire visible spectrum of light. Such broadband antireflective coatings are especially interesting for optical elements like lenses.

The systematic analysis of ever-increasing data collection presents companies with ever-greater challenges. Many manufacturing organizations simply lack the know-how to handle Big Data projects and the corresponding data analysis right. Therefore one simply follows the current trends and buzz words and adopts approaches which are currently en vogue. This approach often leads to less successful projects and several regularly reoccurring patterns of misconceptions can be identified. This paper highlights some of these unsuccessful patterns and introduces some of the work done in the PRO-OPT SMART-DATA research project. The innovation in this data analysis approach is the combination of traditional statistical methods with new Big Data and AI analysis techniques applied to high tech manufacturing. Being able to align process data with the complete metrology data provides amazing new insights into the manufacturing. Furthermore, we will introduce a new visualization technique specifically suited for domains with high amounts of categorical data like semiconductor, photovoltaics, electronics and such. This paper will show how the combination of the statistical data analysis system Cornerstone in conjunction with Apache Spark1 and Apache Cassandra2 provides a good basis for engineering analytics of massive data amounts. By properly nesting the solid mathematical methods in Cornerstone with big data-appropriate infrastructure such as Apache Spark and, in our case, Apache Cassandra, many new analytics issues can be addressed. Analyzes that used to be inefficient due to the sheer volume of data in classically modeled schema’s can now be performed through appropriate big-table modeling and provide the ability to provide completely new insights into production data. Those directly impacted the manufacturing procedures and improved the products quality and reliability. Experiences gained in the project impacted the upcoming VDI/VDE guideline 37143 to be published later in the year 2019.

Low dose scanning electron microscope (SEM) images are an attractive option to estimate the roughness of nanos- tructures. We recently proposed two deep convolutional neural network (CNN) architectures named “LineNet” to simultaneously perform denoising and edge estimation on rough line SEM images. In this paper we consider multiple visualization tools to improve our understanding of LineNet1; one of these techniques is new to the visualization of denoising CNNs. We use the resulting insights from these visualizations to motivate a study of two variations of LineNet1 with fewer neural network layers. Furthermore, although in classification CNNs edge detection is commonly believed to happen early in the network, the visualization techniques suggest that important aspects of edge detection in LineNet1 occur late in the network.

Using high-resolution extreme ultraviolet interference lithography (EUV-IL), we investigated contact hole/pillars printing performance of several EUV resist platforms for the high-NA EUV lithography. We compared the dose and local critical dimension uniformity (LCDU) of the three chemically-amplified resists (CARs) with the best performance for printing contact holes (CHs) at half pitch (HP) of 24 and 20 nm. One of the CARs showed the lowest LCDU, 2.3 and 2.2 nm with lowest dose 16.4 and 21.1 mJ/cm² for HP 24 and 20 nm, respectively. With the inorganic resist we obtained 38.8 mJ/cm² with an LCDU of 1.3 nm for HP 20 nm pillars. We have also studied the effects of the resist thickness and post-exposure baking (PEB) temperature on the dose and LCDU. These results show that there are promising CAR and non-CAR resists for CH printing towards high-NA EUVL.

Defectivity in EUV scanners gains much more importance as they move towards the high-volume manufacturing. The reticle (mask) needs to be protected from particle contamination, both inside and outside the scanner environment. One widely used method to realize this is to make use of a thin protective layer on top of the mask, which is called pellicle. In this work we investigate the impact on printed features caused by particles laying on top of the pellicle for a High-NA EUV scanner. The study was supported by simulations using the most up to date High-NA EUV scanner projected design. The most relevant lithographic metrics (namely, change in Critical Dimension, Normalized Intensity Log Slope, dose sensitivity, non-Telecentricity, Pattern Shift and Mask Error Enhancement Factor) have been considered in the study. An experimentally calibrated simulation model is used to predict the particle transmission as function of the particle size. The goal is to set a well-reasoned (based on imaging requirements) maximum particle size specification for production of pellicles and cleanliness inspection. Some sets of mask patterns and sources (use cases) that likely will be used in high volume manufacturing are considered. Furthermore, a comparison with existing 0.33 NA EUV simulation results is done.

EUV lithography is being used at relatively high-k1 Rayleigh factors. Advancing EUV to smaller resolution requires several technological advancements. The EUV reticle is a strong contributor that limits current EUV imaging performance. Improvements with advanced mask types are required to reduce mask 3D effects and to improve image contrast. This will enable low-k1 resolution with reduced stochastic defect rates. In this paper we discuss what the requirements of high-k absorber masks and attenuated phase shift masks are to achieve optimal imaging performance. Recommendations on the mask stack composition and the application of mask types to different use cases are based on the physical understanding of the mask diffraction spectrum.

The purpose of pellicles is to protect reticles from particle contamination, thus reducing the number of defects and increasing yield. In this paper we show how recent progress in pellicle technology has succeeded in solving the main challenges in imaging with EUV pellicles. We demonstrate this using the recent results of imaging tests in scanner, EUV reflectivity measurements, and lifetime testing. EUV light reflectivity of pellicles is one of the effects that have negatively impacted imaging with pellicles in the past. Light reflected from pellicles leads to the overexposure of neighboring fields in the corners and edges. Tests with pellicles produced using a new process show EUV reflectivity within specification of 0.04%, and measured impact on critical dimension in the corners below 0.15nm for multiple pellicles. Lifetime performance was tested by exposing up to 3000 wafers with a pellicle while periodically assessing the stability of imaging metrics. The lithometrics studies include: critical dimension (CD) and critical dimension uniformity (CDU), and contrast (via line width roughness). DoseMapper, which is an EUV scanner application developed to improve CDU, was applied during the lifetime test. Here we show that it can successfully reduce the pellicle-induced CDU and CDU over lifetime (previously shown to be dominated by pellicle EUV transmission drift). Our results using DoseMapper show that whilst intrafield CDU 3sigma increases over lifetime, it stays comfortably within the 1.1nm NXE3400 ATP specification using DoseMapper.

The problem of haze occurrence in photolithography is one of the most important problems in the lithography industry. Understanding the conditions and mechanisms that generate haze defects provide important clues for preparing pellicle, photomask, and lithography environments for haze-free photolithography. In the pellicle industry, self-help efforts are being made to reduce the contribution of pellicles to haze occurrence, but haze occurs in the complex causal relationship of pellicles, photomasks, and lithography (fab environments). Therefore, haze reduce is difficult to solve with pellicle industry's efforts only. In this paper, we investigated microscopic images and occurrence mechanisms of haze defects formed from actually suspected chemicals, IC results of sulfate and ammonium ions, ArF light (excimer laser) resistance of anodized and new frame, also summarized the results of haze occurrence from previous research, and examined the occurrence pattern and location according to haze cause. Based on this, we propose the pellicle solution to control the haze reduction such as material selection of pellicle.

Wafer Intra-Field Process (Printing) Defects created due to various process segments. Narrow Lithography process window (Litho PW), effected by Dose & Focus (calibrated by FEM – Focus Exposure Matrix), is one of the major contributors for the wafer intra-filed process defects caused by hot spots. The Litho PW can be expanded by controlling the Dose parameters over the wafer intra-field. Dose parameters effect the Critical Dimension Uniformity (CDU). Controlling the wafer intra-field CDU will expand the Litho PW and will reduce the process (printing) defects. The extension of 193nm based lithography usage combined with design shrinkage rules for process control (in particular the wafer level CDU control), are extremely important and challenging task in IC manufacturing. This work will show the ZEISS CDC application (CD Control) and its significant positive effect on the intra-field CDU, Litho PW, and process defects probability, as well as introduction for wafer FAB integration flow. It will also challenge some existing process parameters specifications and will explain why IC manufacturing failures come real although all individual process parameters in spec. Specification limits for each individual parameter do not necessarily guarantee a successful process, as it’s almost impossible to anticipate and verify all possible interdependencies among different parameters. The goal is therefore, to show how to improve IC process by shrinking its individual parameters distributions, even if the variability of those parameters is in specification. This work will offer solution named as “Excursion Prevention” - Improve wafer intra-field CDU by using the ZEISS CDC tool, to reduce the wafer intra-field printing defects caused by narrow Litho PW.

The result of electron beam lithography is influenced by many effects: forward and backward scattering, formation of secondary electrons, re-scattering of electrons, chemicals diffusion in the resist material, wafer stack, etc. To achieve high resolution all these effects should be taken into account. Commonly, the electron energy distribution in the exposed matter is described by the Point Spread Function (PSF). This is a simple approach which takes into account large portion of phenomena using few parameters. PSF function is a Gauss or multiple Gauss function, which is determined experimentally by the calibration procedure. Each resist material with corresponding stack is characterised by its own PSF, in case of double Gaussian, with the following parameters: α, β and η. In the current work the PSF parameters were systematically varied to study their influence on the dose assignment and resulting pattern. This gives a broader understanding of the correction mechanism using PSF. Furthermore, the resulting shape of the structure is influenced not only by the PSF parameters and dose assignment, but by the fracturing type as well. All these effects were studied using experimental and simulation approaches.

Every advance in technology node challenges the semiconductor industry to achieve even tighter on-product overlay (OPO) requirements. With the latest immersion scanners performing well below the sub-2-nm overlay level, the OPO budget is more and more determined by non-lithography contributors. Achieving the tight overlay specifications in a high-volume manufacturing environment is therefore far from trivial, especially in the wafer edge region where processing is even less well controlled. For example, Reactive Ion Etch (RIE), the deposition of stressed thin films and the presence of significant intra-field (or intra-die) stress distributions are all known to cause localized distortions in the wafer edge region. Annealing steps during integrated circuit manufacturing are another source of wafer deformation. Furnace anneal is one particular type of annealing step. During furnace anneal processing, many wafers are heated-up simultaneously and wafers stay at elevated temperatures for a fixed time on the order of minutes to hours. Although in general, furnace anneal does not cause significant wafer deformations, local distortions are sometimes observed in the wafer edge region by using standard boats at higher anneal temperatures. In this work, we have setup a controlled experiment to characterize the local distortions that can be induced by furnace anneal processes. To this end, wafers are processed with various furnace anneal settings, i.e. temperature and ramp rate, and two different boat types are used. The induced distortions are accurately and densely measured on an NXT:1970Ci scanner using its SMASH alignment system. We will see that, depending on the process conditions and boat type, local distortions occur at the wafer edge. The locations of these distortions coincide with the wafer support positions of the boat and therefore they are also referred to as boat marks. Several solution directions for mitigating furnace anneal induced distortions will be discussed. A very effective solution is the employment of an optimized boat design that, depending on the process conditions, can prevent the localized distortions at elevated temperatures. It would therefore be beneficial to have a detection system in place that can detect and consequently trigger actions to mitigate furnace anneal induced distortions during the development phase of anneal processing steps. We will demonstrate that the scanner can be used as such a detection system as its inline metrology is able to detect signatures related to the boat marks.

The goal of the conducted work was to fabricate chrome masks on Al₂O₃ substrates, which could be successfully applied to UV and DUV lithography. The technique is based on electron beam lithography and wet chrome etching in an ceric ammonium nitrate solution. The main advantage of the proposed fabrication method is a major decrease in exposition time due to more effective usage of electron energy. We will demonstrate the use of low electron energy exposition methods with PMMA/MA resist with applied doses of a few μC/cm². To the best of the author’s knowledge, sapphire substrates have not been previously used in photomasks fabrication. So far, full photomasks sets based on Al₂O₃ substrates have been manufactured and applied to fabricate the pilot series of acoustic transducers in the AlGaN/GaN heterostructure for piezotronics applications.

Publisher’s Note: This paper, originally published on 29 August 2019, was replaced with a corrected/revised version on 24 February 2020. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.