This PDF file contains the front matter associated with SPIE Proceedings Volume 10958, including the Title Page, Copyright information, Table of Contents, Author and Conference Committee lists.

University fabrication facilities that are both open and shared were created to enable far wider access to tools and methods previously only available to faculty at a few select universities. The lab now known as the Cornell NanoScale Science and Technology Facility (CNF), was the first NSF-supported national user facility in this field about 42 years ago. This talk will consider how open and shared facilities have evolved, and how important it has been to both academic and industrial research in the US. Flexibility and measured changes make CNF and its partners in the National Nanotechnology Coordinated Infrastructure (NNCI) even more relevant going forward as we see technical challenges that must be met due to the explosion in interdisciplinary fields. Some of the needs we see for the future, surprisingly, will have many synergies with the semiconductor industry.

Background: Moore’s Law has to-date governed the economics of lithography-driven scaling in semiconductor manufacturing, where lithography tools provide higher resolution and smaller addressable pixels while maintaining high throughput and lower cost per pixel. On the other hand, Tennant’s Law describes how lithographic throughput decreases dramatically as resolution is improved for a wide range of lithographic approaches.
Aim: Why is there a disconnect between the optical lithography that has enabled decades of Moore’s Law behavior and the many other lithographic techniques that seem to follow Tennant’s Law?
Approach: The answer lies with the concept of stochastic-limited lithography. By developing very simple scaling relationships, a physical explanation for Tennant’s Law can be provided. By applying this explanation to optical lithography, its past can be explained and its potential for future success examined.
Results: While optical lithography has not been stochastic-limited in the past (thus allowing it to avoid the fate of Tennant’s Law), in the future it will surely become stochastic-limited.
Conclusions: The answer to the title question “Will stochastics be the ultimate limiter for nanopatterning?” is clearly yes whenever throughput plays an important role in economic viability.

The design and implementation of metasurface-based flat lenses have come to the forefront of ongoing scientific research and technology development. These novel photonic devices use sub-wavelength metal or dielectric resonators spaced on a specific two-dimensional pattern that mimic the phase profile of conventional bulk optical elements. However, most of these structures, or metasurfaces, have so far been passive with its optical performance determined only by the spatial configuration of the metasurface constitutive elements. The development of dynamic metasurfaces is currently a growing area of research directed to obtain real-time tunable operation of metasurfaces and new physical phenomena not feasible with static metasurfaces. Faster reconfigurable metasurfaces can be achieved by incorporating nanostructures with different optical response onto MEMS based actuators. The MEMS-metasurface platform enables electrostatic control of curvature, tilt angle and deformation of metasurfaces, enabling flat and agile optical elements with micro-second reconfiguration time. These unique dynamic metasurfaces may provide new opportunities for information optics and imaging by performing complex signal processing directly in the optical domain. In this presentation, I will describe the fundamentals and advantages of incorporating metallic and dielectric metasurfaces onto MEMS devices and the challenges associated with their patterning and integration.

We use the term “single-digit nanofabrication” (SDN) to describe the structuring and characterization of materials whose key features are defined and resolved on a scale of 10 nm or less. Achieving single-digit nano resolution in synthesis and fabrication is a central challenge for the development of next-generation functional nanoscale and mesoscale materials Single digit nanostructured materials have special properties with regard to the control and flow of energy. Energy can take, for example, electronic, magnetic, thermal or photonic forms. We will focus on how material components can be structured with high accuracy and precision in classical lithographic processes 2D and how we can achieve new or improved properties in 3D fabrication. One of the field that requires such precision, resolution and control of materials is nanophotonics. Nanophotonics covers light interactions with dielectric materials and plasmonic effects in metallic structures. In addition, we have emerging efforts in exciton transport in organized nanomaterials. PLASMONIC LIMITS Gap Plasmonic antennas are of great interest due to their ability to concentrate light into small volumes. Smaller the volume higher is the enhancement until the gap is so closed that other effect start to became more important. Theoretical studies, considering quantum mechanical effects, have predicted the optimal spatial gap between adjacent nanoparticles to be in the subnanometer regime in order to achieve the strongest possible field enhancement. We developed a technology [1] to fabricate gap plasmonic structures with subnanometer resolution, high reliability, and high throughput using collapsible nanofingers. The systematic investigation of the effects of gap size are consistent with previous findings as well as with a straightforward theoretical model that is presented here. LARGE AREA METASURFACES Metasurfaces have facilitated the replacement of conventional optical elements with ultrathin and planar photonic structures. Previous designs of metasurfaces were limited to small deflection angles and small ranges of the angle of incidence. We have created two types of Si-based metasurfaces, [2] working both in transmission and reflection modes, to steer visible light to a large deflection angle. These structures exhibit high diffraction efficiencies over a broad range of angles of incidence. We have demonstrated metasurfaces based on conventional thin film silicon processes that are suitable for the largescale fabrication of high-performance devices. EXCITONIC PROPERTIES OF DIRECTED ASSEMBLY PEROVSKITE NANOCRYSTALS Colloidal nanomaterials display a broad range of unique chemical and physical properties that make them prime candidates as nanoscale building blocks for the development of future technologies. Towards this goal, one of the main challenges resides in developing methods to manipulate these materials with a level of precision comparable with their small size. We studied the effects of topography and surface chemistry on the assembly behavior of perovskite nanocrystals PNC [3] with outstanding optical properties and great potential for applications in optoelectronics and photonics. Arranging PNCs in 1D-like features allows careful studies of the collective mechanisms of exciton diffusion and recombination in PNCs assemblies, which in turn determine the optoelectronic behavior of the system and offer fundamental guidance in engineering new optoelectronic devices made of PNCs. Work was supported by the Office of Science,Office of Basic Energy Sciences, of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231. [1] Boxiang Song et al “Probing Gap Plasmons Down to Subnanometer Scales Using Collapsible Nanofingers”; ACS Nano, June 2017 [2] Dianmin Lin et al ”Optical metasurfaces for high angle steering at visible wavelengths”; Scientific Reports 7, Article number: 2286 (2017) [3]L. Protesescu et al. Nano Letters 15 (2015) 3692-3696

Multi-photon lithography (MPL) remains among the handful of practical techniques that can be used to fabricate truly three-dimensional (3D) micro- and nanometer-scale structures with few processing steps. Although photopolymers remain the primary material system for MPL, others have been developed for creating functional structures in chalcogenide glasses and polymer-composites. Post-exposure processes have been developed for transforming a structure created by MPL into another material, such as a metal, semiconductor, or oxide glass. MPL has been used to create a wide range of functional nanophotonic devices. The full potential of MPL is apparent in its use to create spatially-variant lattices (SVLs). SVLs are a new class of nanophotonic device that is engineered to direct and control the flow of light in 3D. The devices are based on unit cells that control the propagation of light through the selfcollimation effect. These unit cells are spatially varied in orientation throughout an SVL so that light flows along a prescribed path within the device. The geometry and patterns of the unit cells within the lattice can also be varied to control other key properties, such as phase and polarization. SVLs and their fabrication by MPL opens a new route to 3D integrated photonics, and a myriad of other applications.

Self-assembled rolled-up microtubes are exploited to rigorously compact 2D devices into 3D microarchitectures. We demonstrate integration of transistors, integrated circuitry as well as electronic, photonic and magnetic components into microtube devices for sensor arrays and novel device platforms such as lab-in-a-tube systems. In combination with self-wound energy storage units our work bridges lengthscales for a new generation of high performance electronic microdevices.

The advance in microlithography has greatly helped the development of micro optical elements. Large array of microlenses can now be fabricated in the same fashion as manufacturing of integrated circuit at low cost and high yield [1-2].
Because microlens array requires well-defined and continuous surface relief profile, special methods are needed to supplement the normal microlithography to produce those spherical structures [3]. Various techniques have been developed, and the most widely used is multi-step photolithography with thermal resist reflow. However, the alternative grayscale photolithography technique appears to be the one as the most flexible and versatile method [4].
Indeed, this approach is a one-level lithography process enabling the development of 3D profiles in a photoresist masking layer. In addition, with the need to maintain or improve image quality at an ever-smaller pixel size, grayscale technic can offer one way to compensate the loss of the photosensitive area by achieving zero-gap microlens. One other advantage of grayscale is the possibility to have, from a single lithography, objects of different shapes, but also at the same time of different sizes (especially heights); which is possible with classical lithography only by doing multi-patterning.
There are several options for performing grayscale lithography, for example the HEBS mask (high energy beam sensitive) which darkens under exposure to electrons. The option that has been chosen is to use a grayscale reticle, with varying chromium features densities that locally modulate the intensity of transmitted UV light. Being non-uniformly exposed, this allows the creation of a relief structure in the resist layer after development. The resist height after development depends on the intensity of the incident light, the exposure time and the contrast of the resist. So contrary to conventional lithography where the goal is to achieve straight resist pattern profiles, grayscale lithography enables the realization of progressive profiles, which requires smooth resist contrast curve. The other specificity of these resists is that they must crosslink without flowing.
In this paper, we evaluate resists from different suppliers to generate microlenses smaller than 5μm via a grayscale mask. The study consists in establishing the contrast curves of these resists according to different process parameters, giving the designer great control of grayscale levels that can be achieved for a given resist. Then, pattern various microlenses shapes in these resists to evaluate the residual resist thickness according to the gray levels. With the final objective of establishing a relationship between these contrast curves and the profile variations at the microlens level to compute a suitable and accurate grayscale mask [5].

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. On test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was demonstrated. SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications. Comparable results were also achieved on device wafers by applying a multi-wavelength alignment strategy and a feed forward strategy to realize align signal convergence within the allocated 0.60 second budget.

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid, which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Overlay budgets play a large role in defining production readiness. As an example, DRAM devices require overlay on the order of 20% of the half pitch. Canon uses a through the mask (TTM) alignment system to measure a Moiré image anywhere in the field. This system can also record alignment errors of all fields and all marks. The data collected by the TTM system correlates very closely with an Archer measurement tool. In addition, a High Order Distortion Correction (HODC) system, which applies a heat input on a field by field basis through the use of a DMD array has been combined with magnification actuators to correct high order distortion terms up to K30. There is an additional distortion term that must also be addressed for the case of nanoimprint lithography. NIL drop patterns are typically designed to minimize resist fill time and create a uniform residual layer beneath the resist pattern. For device wafers, however, it is important to recognize that there are both long wavelength flatness errors coming from the wafer chuck and existing pattern topography from previously patterned levels that cause out of plane errors. When the mask comes in contact with the resist on the wafer, these out of plane errors can then induce mask bending, resulting in an additional distortion term. To minimize this distortion, a Drop Pattern Compensation (DPC) Model has been implemented to minimize the added distortion terms. In this paper we describe the origins of the out of plane errors, and describe the model used to correct these errors along with some examples. Finally, results are presented for a device like wafer in which the overlay errors within a field are reduced from 5.4nm to 3.4nm, 3 sigma.

We will introduce SCIL as a full-wafer soft-stamp base nanoimprint technique with the advantages of being able to replicate sub-10nm features and perform micron accurate overlay alignment over 200mm wafers. The combination of PDMS based soft stamps and an inorganic crosslinking imprint resist leads to a very long stamp lifetime and the direct patterning of complex deep sub-micron patterns, such as slanted gratings with an index up to n=2.1. These complex patterns are of high interest for nano-photonic enabled applications such AR/VR and metasurfaces with applications such as “perfect” flat lenses. A new analytical model based on hyper-elastic deformation of silicon rubber nano-patterns was developed and is able to accurately predict pattern stability from sub-micron to less than 20nm patterns.

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates. ^[1][2][3] NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. The challenges of NIL implementation for mass-production are overlay, defects, throughput, template life, and template patterning. The overlay and defects must satisfy the requirements of the products applied. The throughput needs to provide adequate cost of ownership (CoO). Since NIL is a contact process, its template damage by the particles on a wafer is inescapable and a longer template life is required for mass production.[^4]-[10] In our previous study, we have reported that the hp2xnm NIL process performance is getting closer to the requirement for the high volume manufacturing. We focused on the process overlay accuracy and demonstrated dramatic reduction of process overlay error by using CVA(controlled viscosity alignment) and HODC(high order distortion control) function of FPA-1200 NZ2C. ^[11] Currently, we have further developed a nanoimprint lithography (NIL) technology including NIL system, template, and resist process for half pitch 14 nm direct pattering. The hp14 nm template was fabricated by a self-aligned double patterning (SADP) on a template. Using this template, we fabricated hp 14 nm dense Si lines with a depth of 50 nm on a 300 mm wafer. In this paper, we report on the latest lithography performance of NIL including hp14nm pattering with single mask exposure.

Mapper has installed its first product, the FLX–1200, at CEA-Leti in Grenoble (France). This is a maskless lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. The FLX-1200, containing 65,000 parallel electron beams, has a 1 wph throughput at 300 mm wafers and is capable of patterning any resolution and any different type of structure all the way down to 28 nm node patterns. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion system using standard NVSM marks. Mapper Lithography and CEA-Leti are collaborating to develop turnkey solution for specific applications. In figure 1 the basic operation principle of the Mapper technology is shown. The electron optics have no central crossovers making them intrinsically insensitive to Coulomb forces (electron repulsion). The electron optics are modular and much cheaper than high-NA DUV optics, and can be replaced or upgraded in the field. The wafer exposure happens one column of fields at a time and always in the same direction. There is no need to meander. The focus and leveling is performed during stage fly-back to reduce metrology overhead. Each column of fields is aligned separately, with dedicated alignment targets. Figure 1, Basic operation of the Mapper technology. In figure 2 the way the beams are distributed over the electron optics slit is shown. The writing strategy is as follows: - There are up to 5 slits, staggered in X direction for reasons of wafer coverage. The approach is roughly analogous to an inkjet printer - Each slit area consists of 204 x 13 individual groups of beamlets, organized in a hexagonal array. - All beamlets are simultaneously horizontally deflected over a range of 2µm while the wafer is scanned vertically. - Each group comprises 49 individual beamlets (7x7). Each of the 49 beamlets can independently be switched on and off during exposure. - Each beamlet results in a Gaussian spot on the wafer with 25 nm FW50 diameter (10.6nm 1). - Total beamlet count will therefore equal 5 x 204x13 x 49 = 649,740. In the FLX-1200 and FLX-1300 the central 10% are used (one half slit area): 65,000 A more detailed description of the principles of operation is given in [2]. Figure 2,Distribution of the beams over the electron optics slit. The focus of presentation will be the reporting of the performance achieved of the tool installed at CEA-Leti during endurance runs in full tool configuration. This includes status of: - Exposure throughput - Achieved resolution and CD uniformity - Stitching performance - Matched Machine Overlay - Tool availability and uptime Also the different application areas for such a maskless system are discussed. In figure 3 a preview of a CD uniformity measurement result is shown. On a 300 mm wafer fields of 5mm x 5mm have been exposed containing 60nm dense lines and spaces. The main source of CD variation is caused by differences between the groups of beamlets. To measure this variation we have taken 824 SEM images, each taken of a pattern written by a different beam group. The result is shown in figure 3. The variation is 8nm 3s, and follows a Gaussian distribution of 6nm 3s. Figure 3, Distribution of 824 CD measurements results on 60nm dense lines and spaces

A multi-beam mask writer MBM-1000 is developed for the N5 semiconductor production. It is designed to accomplish high resolution with 10-nm beam and high throughput with the 300-Gbps blanking aperture array and inline corrections. It inherits dose correction functions for secondary dose from scattered electron which has been used with single variable shaped beam (VSB) writers with full compatibility. It also has new corrections in scale shorter than 10 um to cope with electron backscattering occurring with EUV substrates and CD bias from resist process. To improve patterning resolution, pixel level dose correction (PLDC) is implemented to correct and enhance profile of dose deposited in resist. Writing test with pCAR showed that PLDC solves breakage and loss of assist patterns without affecting shape and size of main patterns.

Publisher’s Note: This video, originally published on 16 August 2019, was withdrawn per author request.

The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). Functional electrical testable Via-Chain structure is fabricated to verify the integrity of the proposed method. Through the analysis of the observed failure modes, the process is further improved. By validating DSA for such an important patterning element as metal cut, the DSA maturity can be further advanced and hopefully move DSA closer to HVM adoption.

Directed Self-Assembly (DSA) of Block Copolymer (BCP) is a promising lithography approach to achieve high resolution pattern dimensions. The current chemo-epitaxy process used to induce block copolymer self-alignment is showing today its limitations. This is due to the resolution limitation of conventional lithography technics needed for the guide formation, used to achieve BCP alignment. This paper introduces a new chemo-epitaxy process, named ACE (Arkema-CEA), which is based on sidewall image transfer (SIT) patterning. This process has the great advantage to offer guides of small critical dimension (CD) and pitch that allows the integration of high χ BCP. In this paper, different parameters of the ACE process are investigated (commensurability, spacer CD …) in order to precisely determine the DSA process window defining the best conditions for BCP alignment. Process window with multiplication factor ranging from 2 to 4 are obtained on BCP under investigation.

Lithographic and pitch-multiplying spacer technologies are widely used to shrink interconnect periodicity within critical layers. This places significant burden on overlay and CD uniformity of the subsequently patterned vias to physically contact and electrically connect critical layers to the rest of the integrated circuit in a nearly defect-free and perfectly-consistent manner. We are evaluating the combination of EUV and DSA patterning technologies to meet this challenge and enable future technology nodes. The contact hole guide pattern is fabricated atop bilayer hardmask material by single-exposure EUV, surface-modified with telechelic polymer brush materials, and finally shrunk/rectified using self-assembled, lamella-forming polystyrene-block-polymethylmethacrylate (PS-b-PMMA). The nascent via pattern is then blanket exposed by DUV light and the photolyzed PMMA is selectively rinsed away. Here we study the process performance of DSA pattern wet etch chemistry and subsequent dry etch pattern transfer into bilayer hardmask material using both metrology and electrical yield measurements as evaluation criteria. In particular, the choice of wet etch solvation strength selective towards PMMA was varied from moderate (isopropanol, IPA) to good (acetic acid, AAc). Due to the ability of AAC to solubilize all covalently-untethered PMMA, regardless of molecular weight, the resulting average CD is wider and its local distribution is more uniform. In contrast, IPA is only capable of rinsing away the smallest PMMA fragments, resulting in relatively tighter bounds about the preferable blanket UV dose, and a smaller average CD and less-uniform local CD distribution. These morphological differences are confirmed by cross-sectional transmission electron micrographs. Brightfield inspection and inline electrical testing are used to compare relative defectivity and yield, respectively, to assess the potential impact on device performance for processes utilizing either solvent.

The development of various forms of super-resolution microscopy have paralleled the resolution gains in lithography. From micron limited resolution 30 years ago, to nm resolution today. In biology, the fundamental direction has been to work towards increasing fine structure in the absence of pitch shrink—a fundamentally similar problem to modern lithography. There are a variety of supper-resolution techniques—depletion based, interferometric, harmonic, and multicolor. From a theoretical perspective, both problems are bound by information transfer limits in the system and ultimately by noise.

Alternative lithography approaches, especially pattering technologies are in advance since several years. Every day new, more or less high localized, AFM-tip based structuring methods as well as new optical and e-beam methods become acquainted. Most of them are sequential single-point procedures. The local interaction reaches from 150 nm up to sub-10 nm. Especially tip based methods are developed on the basis of atomic force microscopes AFM. Therefore, the ranges, which can be structured, are only in the range of 2 µm x 2 µm up to 100 µm x 100 µm. In most cases it is not known or not verified if those new tip based techniques are suitable for larger ranges and areas. Even the stages and control algorithms of AFM’s are not optimized for defined, high dynamic and as well high stable scanning trajectories in the nanometre respectively in the sub-nanometre level. Here, Prof. Tseng from Arizona State University noted “the quality…of the nanostructures created by TipBased Nanofabrication depend greatly on the capacities of equipment and instruments used and the extent to which the tip can be precisely controlled. It is unavoidable that the TBN system be automated and that precision of control be in the subnanometers for dimension accuracy, and sub-nanonewtons for force accuracy.” [1] A first way out to increase the precision could be the application of so-called metrological AFM, especially developed at national metrological institutes. But the deficit of a small scanning range still remains. Nanopositioning and nanomeasuring machines where developed at the Technische Universität Ilmenau, Institute of Process Measurement and Sensor technology, first for positioning and measuring three-dimensional objects in a range of 25 mm x 25 mm x 5 mm with 20 pm resolution and nanometer precision [12]. They can equipped with most versatile probing systems like AFM, laser focus probes and 3D-micro probes to fulfill extraordinary metrological challenges. This unique precision is allowed by the application of an extended three-dimensional Abbe-comparator principle combined with high precision laser interferometer controlled stage in six degrees of freedom. A substantial progress in nano patterning can be achieved by combining this outstanding technology with advanced scanning proximal probe lithography on the base of Fowler-Nordheim-electron-field emission [30]. In this NPMmachine the high precision large area pattern generation can be combined with an advanced high speed nanometrology simultaneously. This paper addresses different aspects that are related to the metrological challenges in increasing measuring volumes up to 200 mm x 200 mm x 25 mm, high dynamic nanopositioning and control on complex trajectories, as well as implementation of nanofabrication tools into the NPMM-machine.

This paper reports the modelling, simulation and fabrication process of a novel heated atomic force microscope (AFM) cantilever. The fabricated cantilever is used for thermal dip pen nanolithography (t-DPN) applications where the heated AFM cantilever can deposit molten polymer. The ability to control the flow of the molten polymer via thermocapillary force during pattering is limited in current heated AFM cantilevers. We present a new design of the heated AFM cantilever to improve the patterning speed and provide the ability to control the flow rate of the polymer. In this paper, we focus on the nanofabrication part to explain different semiconductor fabrication process development and integration for manufacturing the heated AFM cantilevers.

Digital Light Synthesis (DLS) is a breakthrough 3D printing/additive manufacturing process pioneered by Carbon (Science, 2015) that uses digital light projection, oxygen permeable optics, and programmable liquid resins to manufacture high-performance, durable final polymeric products. DLS pairs the resolution and detail of light-based technologies with the material properties and durability of heat-based forming technologies. This talk will give an overview of the DLS process as it stands today, with an emphasis on the materials developed and qualified to meet the unique demands of applications in a variety of industries.

Advances in lithography and nanofabrication have long been driven by the requirements of the classic Von Neumann architecture. As Moore's Law comes to its end and advances in computing shift the market's demand for computing towards AI, entirely new architectures, neuromorphic architectures, are coming into vogue. The different requirements of neuromorphic computers, including enormous demand for memory and a high tolerance for defects, requires a reassessment of what is and is not feasible in IC manufacturing. Alternative approaches to lithography and fabrication, such as directed self-assembly, which suffer from high rates of defectivity incompatible with conventional architectures, may be necessary to build the most complicated and dense future architectures conceived. We will review the different requirements for a range of future architectures based on novel nanotechnology and some of their use cases in neuromorphic computing. We will show that while some approaches, such as GPU replacements which seek to accelerate vector matrix multiplication, have many of the same manufacturing requirements as existing conventional computers, other, memory intensive architectures have different tolerances for defectivity depending on the nature of the defects and the use case. For crossbar topologies, different strategies can be used to tolerate row and column defects as well as point defects on individual devices. The different use cases involving inference, ex-situ training, in-situ training, supervised and unsupervised learning each also have distinct regimes of defect tolerance, with ex-situ trained systems being the least tolerant and unsupervised, in-situ trained systems being the most tolerant. With directed self-assembly also having a large dynamic range of defect densities (0.1%-10%), we use estimates of defect tolerance from the established literature to intuit approximate regimes of usefulness for different technologies. Understanding the limits of defect tolerance in these systems is especially important given the increasing memory density demands of neuromorphic architectures requiring monolithic 3D integration of logic and memory. Manufacturing multiple stacked layers at the smallest feature size can become cost prohibitive due to the large number of critical mask steps. With a neuromorphic architecture however, operating in the most tolerant use case to defects, it may become possible exploit advances in 3D assembly to realize the largest and most complex computing architectures based on unsupervised learning of unstructured data.

Crossbar arrays of resistive non-volatile memories (NVMs) offer a novel and innovative solution for deep learning tasks which are typically implemented on GPUs [1]. The highly parallel structure employed in these architectures enables fast and energy-efficient multiply-accumulate computations, which is the workhorse of most deep learning algorithms. More specifically, we are developing analog hardware platforms for acceleration of large Fully Connected (FC) Deep Neural Networks (DNNs) [1,2], where training is performed using the backpropagation algorithm. This algorithm is a supervised form of learning based on three steps: forward propagation of input data through the network (a.k.a. forward inference), comparison of the inference results with ground truth labels and backpropagation of the errors from the output to the input layer, and then in-situ weight updates. This type of supervised training has been shown to succeed even in the presence of a substantial number of faulty NVMs, relaxing yield requirements vis-à-vis conventional memory, where near 100% yield may be required [2]. We recently surveyed the use of analog memory devices for DNN hardware accelerators based on crossbar array structures and discussed design choices, device and circuit readiness, and the most promising opportunities compared digital accelerators [3]. In this presentation, we will focus on our implementation of an analog memory cell based on Phase-Change Memory (PCM) and 3-Transistor 1-Capacitor (3T1C) [4]. Software-equivalent accuracy on various datasets (MNIST, MNIST with noise, CIFAR-10, CIFAR-100) was achieved in a mixed software-hardware demonstration with DNN weights stored in real PCM device arrays as analog conductances. We will discuss how limitations from real-world non-volatile memory (NVM), such as conductance linearity and variability affects DNN training and how using two pairs of analog weights with varying significance relaxes device requirements [5, 6, 7]. Finally, we summarize all pieces needed to build an analog accelerator chip [8] and how lithography plays a role in future development of novel NVM devices. References: [1] G. W. Burr et al., “Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element” IEDM Tech. Digest, 29.5 (2014). [2] G. W. Burr et al., “Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses) using phase-change memory as the synaptic weight element”, IEEE Trans. Elec. Dev, 62(11), pp. 3498 (2015). [3] H. Tsai et al., “Recent progress in analog memory-based accelerators for deep learning”, Journal of Physics D: Applied Physics, 51 (28), 283001 (2018) [4] S. Ambrogio et al., “Equivalent-Accuracy Accelerated Neural Network Training using Analog Memory”, Nature, 558 (7708), 60 (2018). [5] T. Gokmen et al., “Acceleration of deep neural network training with resistive cross-point devices: design considerations”, Frontiers in neuroscience, 10, 333 (2016). [6] S. Sidler et al., “Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: impact of conductance response”, ESSDERC Proc., 440 (2016). [7] G. Cristiano et al., “Perspective on Training Fully Connected Networks with Resistive Memories: Device Requirements for Multiple Conductances of Varying Significance”, accepted in Journal of Applied Physics (2018). [8] P. Narayanan et al., “Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory”, IBM J. Res. Dev., 61 (4), 1-11 (2017).

Historically, ultraviolet (UV) gratings used in astronomical spectrographs have been made using two different techniques. Mechanically-ruled gratings have been produced for more than a hundred years. A diamond tool is used to create parallel grooves onto a fine metallic coating layer that has been previously deposited on a polished substrate. The edge-on profile of these grooves is a sawtooth tilted at a specific angle called the "blaze" angle. The blaze angle is the deciding factor that will allow for maximum efficiency at a specific wavelength called the "blaze" wavelength. Holographic gratings are produced using interference lithography. A layer of photoresist deposited on a substrate is exposed to fringes usually formed by exposure to two coherent laser beams. After development, the resulting pattern is sinusoidal by nature. Blazing one side of the sinusoidal profile of holographic gratings is possible through ion etching, but is only commonly used for a limited subset of grating parameters. Both types of gratings have different advantages: - Ruled gratings have a sharp, blazed profile that ensures good efficiency. However, they suffer from groove spacing inconsistencies that lead to stray light and ghosting. - Holographic gratings do not suffer from groove spacing errors which minimizes stray light. However, their sinusoidal profile (if not ion etched) leads to efficiency losses. At Penn State University, we are studying new processes that allow to fabricate blazed, high efficiency and high spectral resolution UV gratings for astronomical purposes. These processes are derived from the ones we used in creating X-ray gratings and consist of: 1) writing an electron-beam pattern consisting of parallel grooves on a layer of positive resist that has been deposited on a Si substrate. 2) dry etching this profile into a hard mask made of silicon nitride. 3) wet etching with KOH that will create the sawtooth profile at a specific blaze angle thanks to the properties of the different crystallographic planes of silicon. Gratings fabricated using these techniques show an excellent behavior all around, combining the best qualities from both ruled and holographic gratings. Indeed, they display a sharp sawtooth profile, they do not suffer from periodicity errors, and grating facets show low roughness. Recent testing done at UC Boulder shows efficiencies that are close to the maximum, theoretical limit. Combined with the possibility to create custom blaze angles through the use of custom cut Si wafers, this opens the way to new applications in the field of astronomical UV spectroscopy.

In this paper, patterning challenges that led to the fabrication of a first Spin Torque Majority Gate (STMG) device are explored. We have highlighted key process module developments from the Magnetic Tunnel Junctions (MTJs) pillar patterning to dual damascene scheme wiring module. Spin devices such as STMG have already been proposed as a replacement for conventional CMOS transistors. The main challenge to their experimental demonstration remains the successful fabrication of connected MTJs through a ferromagnetic layer, allowing spin transport across the gate. We propose a new etching approach utilizing Ion Beam Etching (IBE), to be able to pattern the MTJs with high precision and with less damage to the magnetic layers. Furthermore, we have introduced Electron-beam lithography to further scale down the device geometries. This development paves the way towards a fully integrated STMG device for Spin Logic applications.

Patterning surface with structural DNA origami mask presents a major interest for nanolithography due to its modularity and high ability to achieve a high resolution with 3-5 nm. In this paper, we demonstrate a sub-ten-nanometer lithography process using anhydrous HF vapor into a SiO2 substrate (figure 1). After optimizing rinsing conditions on SiO2 substrate and HF etching process, we reach a high density (<20 nm pitch) and high resolution (~10 nm CD) patterned surface with a fast etching rate of 0.2 nm.s-1. The resulting SiO2 patterns are used as hard mask in HBr/O2 plasma of Si substrate. Origami pattern features are conserved: lateral dimensions, morphology and structure. For the first time, we developed a high resolution (~10 nm) and high contrast (~65 nm) transfer of patterns into Si substrate. We will highlight the challenges brought by this new technology and demonstrate the feasibility to control this patterning technique. AFM technique has been previously tested to confirm the pattern fidelity. Using all the available imaging capabilities on the CDSEM, we will establish the best method for each layer to achieve the precision required for the targeted nodes of this technology. Beyond the resolution capabilities, the precise placement of the DNA pattern on the substrate is investigated. Based on a pre-patterning step using the nanoimprint technology, the affinity of the DNA with respect to the substrate is locally modified and its influence is analyzed. Thus, DNA origami appears like a promising approach for emerging and engineering of hard mask for patterning.

The manufacturable integration of geometric, equivalent and 3D scaling will drive Future Beyond CMOS devices and information processing technologies and systems. Additionally, interface control and low-energy functional patterning of non-traditional materials will enable the integration of novel heterogeneous 3D materials and systems. For future patterning technologies, resolution and defectivity, as well as line edge and interface roughness continue as key potential show-stoppers. Furthermore, the current resist-based patterning strategy requires a subsequent pattern transfer step, which adds to the stochastic nature and variability of the patterning and pattern transfer processes, and the challenge of achieving low defect sub-10 nm patterns will only increase with each technology generation. The Internet-of-Things era opens an enormous research space and opportunity for exploring emerging research materials (ERMs) that exhibit the potential for achieving sub-8-nm functional feature sizes via the directed self-assembly of novel non-block copolymer (BCP) and nanomaterials. Utilizing intramolecular hydrophilic-hydrophobic interactions as a driving force for self-assembly, we designed and developed a method to fabricate molecular patterning platforms that leverage interactions between bioinspired amphiphilic molecules and various metal cation-conjugates. This system also appears to exhibit a dynamic chi, χ, during the assembly process, which would enhance the formation of highly resolved self-assembled structures. With this method, we were able to demonstrate 2.9±0.8 nm (1σ; n=11) ordered metal/organic line patterns, with a pitch of 7.4±2.0 nm (1σ; n=10), and conductivity through the metal nanowires. While still in the ‘ugly duckling’ stage of development, this study demonstrates the feasibility of achieving self-assembled sub-4 nm functional nanostructures. This breakthrough technology opens the door to new families of self-assembling materials options, with the potential to serve as an inexpensive and effective way to pattern high-resolution features, such as for nanoelectronics, bioelectronics and other emerging 21st century information processing technologies.

The ability to further shrink EUVL geometries can be facilitated using multiple lithographic approaches. Most recent proposals suggest an EUVL double patterning strategy. This path requires additional and expensive EUVL tool time. In our work, using an EUVL patterned polymer as a guide material with DSA incorporated into the lithography flow is an optional process mitigating EUVL tool time. Multiple variations of BCP (block copolymers) were successfully tested. In addition, pattern transfer through silicon containing hard mask and spin on carbon layers was demonstrated with minimum LER (line edge roughness) and good critical dimension uniformity (CDU).

Three-color lithography (3CL) produces features on the scale of tens of nanometers using visible light. In this technique, one beam pre-activates a photoresist, a second beam deactivates it, and a third beam activates the pre-activated regions that have not been deactivated. The deactivation beam trims features, allowing for improved feature size and resolution. Creating permeable thin films enables us to further control feature size using oxygen as a quencher. We will discuss these thin-film studies, which are a promising step towards large-area patterning.

In this work, an evaluation of various adhesion promoters (or primers) for soft ultra-violet (UV) nanoimprint lithography (NIL) is reported. The evaluation is performed using 200 mm wafer scale in the HERCULES® NIL equipment platform available at the CEA-Leti. First, surface energies of the primers are determined through contact angle measurements. Next, atomic force microscope (AFM) measurements were carried out to evaluate the surface uniformity and roughness of the primed wafers. Thin film thickness measurements were performed by spectroscopic ellipsometry in order to select the most promising primer processes for high resolution etch mask and permanent applications. Afterwards, the adhesion layer performances of the selected primer processes were evaluated by an imprint test using a dedicated patterned master (critical dimension down to 30 nm and aspect ratios up to 1.5). Optical and scanning electron microscope (SEM) defect reviews were systematically performed. This evaluation enabled to benchmark several adhesion promotor solutions based on the grafted technology developed by ARKEMA in order to identify an efficient adhesive layer compatible with various NIL resists and substrates, such as silicon based materials or glass.

In recent years, nanoimprint lithography is applied to manufacturing of optical materials and biosensor. However, void and generated gas are caused pattern failures. We proposed cellulose based gas permeable molds to reduce pattern failures. In this research we could raise the mold reproducibility by using the under-layer coating and liquid release agent. It was confirmed that imprinting materials including 10 wt% each of acetone, cyclopentane, and propylene glycol methyl ether acetate (PGMEA) as volatile solvents could also be imprinted accuracy and number of imprinting times were increased. In addition, we succeeded in expand the cellulose based gas permeable mold size 5 times as compared with the conventional cellulose based gas permeable mold by using step and repeat process and large scale quartz mold. Various manufacturing can be expected by increasing the repeatability and the pattern area of the cellulose based gas permeable mold.

Imprinting micro- and nanostructures on non-planar surfaces has gained prominence in various fields such as optoelectronics, photonics and biomedical implants. It has been implemented for applications such as optical sensor arrays and optical fibers. Nanoimprint lithography (NIL) is a low cost, high resolution nanofabrication process. In this work, soft UV-NIL process is used in which a flexible stamp is used which makes it ideal for imprinting on curved surfaces such as plano-convex lens. However, the substrate to stamp positioning for successful transfer of patterns is crucial and needs to be addressed. The Nanopositioning and Nanomeasuring machine (NPMM), developed in the Collaborative Research Center (of the German Research Foundation) of TU Ilmenau, provides a unique solution to the challenges of positioning and alignment. Therefore, a UV-LED assisted small scale NIL-setup was designed, developed and integrated into the NPMM and it was further realized for carrying out fabrication of micro- and nanostructures on silicon chips and planoconvex lenses. In addition to scanning electron microscopy (SEM) and atomic force microscopy (AFM) characterization, the structures were further characterized using a focus sensor. The utilized focus sensor is an optical sensor developed at the Institute for Process Measurement and Sensor Technology of TU Ilmenau. It was observed that the imprinted structures were of considerably good fidelity. Thus, a distinctive integrated imprinting process for flat and non-flat surfaces was developed and implemented.

A high-power LED-based illumination system has been developed as a replacement for the mercury arc lamps used in mask-aligner lithography. LEDs are arranged in a grid array and placed in the entrance aperture of individual reflectors. Those reflectors decrease the angular extent of the light. With this multisource approach, different groups of LEDs can be switched on independently. The illumination patterns created determine the illumination angles and the spatial coherence in the mask plane. The spatial coherence is measured in the mask plane by using a circular double slits approach. The interference pattern for different illumination patterns are measured, showing the effect of the asymmetry and size of the angular extent of the illumination light. The effect of the different illumination patterns on the quality of the prints are also illustrated with print tests.

CMOS imaging has experienced significant developement in the last decades. At the center of this progress lies the pixel, composed of a light sensitive area (photodiode) coupled to a network of transistors. As the pixels sizes shrink, the light sensitive area gets smaller and requires light focusing assistance. To address this issue, microlenses are added to the top of the pixels stack. The microlenses are made of polymer resist transparent to the wavelength of interest. Creating such structures is not straightforward and requires complex process steps, especially when arrays of multiple shapes and sizes are needed. The grayscale approach appears as a promising alternative since this unconventional lithography method can produce variable shapes and sizes in a single lithography step. Mask data preparation is the most critical step for grayscale lithography. A widespread strategy is to experimentally establish the relationship between a given dose (corresponding to a specific chromium density on the mask) and the remaining resist thickness after development. The relationship, also known as contrast curve, is used as a transfer function to compute a suitable mask for the given resist. Our approach is to create a simplified grayscale model able to predict the resist response under any given mask and illumination condition. Using the classic contrast curve approach we have designed a mask composed of sub 5μm patterns and evaluated the resist profile prediction of the contrast curve approach compared to our grayscale model on various patterns including microlenses, pyramids and bowl shapes. Reults show that the contrast curve approach is no longer appropriate when the dimensions reduce below 5μm.

Tilted ion implantation (TII) used in conjunction with pre-existing masking features on the surface of a wafer is a promising cost-effective method for self-aligned double-patterning. Recent work experimentally demonstrated pitch-halving by masked TII into a thermally grown SiO₂ hard-mask layer: the wet etch rate of SiO₂ increases dramatically if the implant-induced damage exceeds a threshold level, so that implanted regions (vs. non- implanted SiO₂ regions) can be selectively removed in dilute hydrofluoric acid solution. In this work, this method is extended to a silicon anti-reflection coating (SiARC) deposited by spin-coating and processed at temperatures compatible with back-end-of-line processing. Negative-tone patterning is achieved by implanting a 10 nm-thick SiARC film with Ar+ species at low energies (less than 5 keV) to reduce the wet etch rate. In general, the higher the implant dose, the greater the etch rate contrast between implanted vs. non-implanted regions of the SiARC layer. In principle, the TII method can be extended to form patterns with dimensions that extend in two orthogonal directions, i.e., two-dimensional (2D) patterns. In this work, the use of TII for 2D patterning is investigated via Monte Carlo simulations to study the effect of implantation dose and varying degrees of overlap between implanted regions extending along orthogonal directions. Stochastic effects on pattern fidelity are systematically investigated. The capability of TII to form sub-lithographic 2D patterns makes it advantageous for extending the era of Moores Law.

NIL patterns frequently suffer from the presence of defects such as missing lines or dots which degrade their properties and functionality. Due to their low density and nanosize, the measurement of their fraction is challenging nanometrology trade-off between resolution and measurement range. In this paper, we focus on the use of range-limited SEM images and explore the benefits of a computational modeling approach to simulate the measurement process and estimate the statistics and accuracy of the measurement of missing lines in patterns. The main questions we address have to do with the choice of the parameters available in the measurement process such as the number of acquired images, their magnification defining the lines included in images and the position (overlapped or not) at line pattern. The missing lines can have both uncorrelated and correlated positions in pattern. In the case of positive correlations, the defects are aggregated whereas in the opposite case of negative correlations they are arranged in periodic-like positions. We found that for uncorrelated defects, the critical parameter is the total number of lines included in the measurement process while the image position do not have any impact on the measurement accuracy. On the contrary, when correlations in defect positions are considered, the number of images and the number of lines per image differentiate their effects on the accuracy of the result while the arrangement of images along pattern also plays a crucial role in the measurement process.