This PDF file contains the front matter associated with SPIE Proceedings Volume 10273, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

This paper sets a framework for those which follow. Specifically, the requirements of lithography and masks are detailed over a 15 year period and the exposure tool roadmap is reviewed. The various business stages in developing a lithography system, from concept to market success, are discussed and the need for earlier involvement of the mask making industry is identified.

In the past, the wafer pattern dimension was same as the mask pattern dimension because 1x exposure tool was widely used until 64KDRAM era. With the introduction of 5x stepper, required mask pattern dimension became five times larger and writing area was reduced as much.

Recently, 64MDRAM and 256MDRAM whose feature sizes are smaller than 0.4μm and required patterning area is wider, require finer geometry and larger patterning area especially considering 4x exposure tools.

In order to lighten both lithography and mask process burdens, new design techniques are considered for new DRAM generations such as COB (capacitor on bit line), IDB(inter-digit bit line) and SWD(split word line driver).

Especially with the improvement of lithography technology using techniques such as phase shift mask and off axis illumination, optical proximity effect is unavoidable by nature. In order to correct this proximity effect, square cornered fine patterns well below the resolution limit of exposure tool are desirable.

In this review, detailed discussion of new technology will not be discussed but related mask making requirement will be discussed instead.

As design rules shrink to meet the needs of advanced chips, the allocation of allowable errors between sources gets ever more critical. This paper will examine the error sources and budgets for current technologies and project the requirements for future 64 and 256 megabit generations.

The emphasis will be on overlay and critical dimension as a function of design rule generation for the photomask, the photolithographic process and the etching process.

Optical wafer steppers are used in the fabrication of submicron and subhalf micron integrated circuits. The SIA Technology Roadmap has outlined the major requirements steppers must meet for the 64M and 256Mbit memory generations. These include 0.35 μm and 0.25 μm resolution over 22 and 27 mm square image fields. This article outlines these requirements and explores the impact on wafer stepper design and use. Stepper cost of ownership will be considered including the contribution of the reticle to the overall cost of the process.

Two major trends can be discerned. First, the requirement of 0.25 μm imaging over fields larger than a square inch forces the adoption of step and scan technologies as the cost and size of full field lenses grow noncompetitive. Second, in order to reduce the overall cost of ownership of the photolithography process, the industry is adopting mix-and-match strategies using high NA steppers to print critical mask layers and high speed, low NA, wide field steppers to print non-critical layers.

Lithography process control is critical for achieving good yield from increasingly complex generations of integrated circuits. Linewidth and overlay control over large die areas are required with smaller errors than ever before. Increasingly complex and expensive equipment and processes are needed to meet these goals. This paper will give an overview of the process engineering issues primarily associated with the 0.35 micron and 0.25 micron generations of integrated circuits. Linewidth control, in particular, will be covered in some detail with emphasis on the effect of the different contributions to focus and exposure variations during patterning. The influence of incoming wafer process variations on the process design for different layers will be described. The challenges of defect density control and throughput and cost control using advanced equipment and processes will be outlined. Mask layout and fabrication issues relating to improved wafer process margins will be discussed. The impact of metrology limitations on the ability to control lithography processes will be described.

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys’ ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

An overview is provided of the technologies and architectures incorporated into commercial pattern generators as they apply to current and expected state-of-theart reticle requirements, and a fundamental assessment and comparison is made of the various approaches being used. The assessments are made with respect to pattern accuracy (pattern placement and feature size), data handling, and throughput; then projected over time in the light of key technical trends and requirements. While at any particular time the comparison of different machine architectures and technologies is heavily influenced by the effectiveness with which they are being implemented, from a fundamental perspective it is shown that raster scan systems have advantages in accuracy and data handling, and vector scan systems have an advantage in throughput. Based on projections of machine technical capabilities it is concluded that both architectures are capable of meeting reticle needs through and beyond the 256M generation of technologies, and that the major challenge is data handling. Most of the necessary performance improvements for all machines are expected to come from processing improvements and from data-path and printing strategy optimization (including multipass printing for error averaging) rather than only from printing-path architectural or hardware improvements.

As the semiconductor industry progresses to 64Mb technology, and beyond to 256Mb, reticle technology will be a major factor in wafer yield. The industry focus is currently on "optical extensions", to the extent that optical lithography may remain the primary technology down to 0.20 pm resolution, and perhaps beyond. For the reticle manufacturer, this translates into dramatically reduced tolerances for critical dimension control, line edge roughness, registration, and defect size. To meet the more stringent criteria, critical process capabilities must advance at a significantly greater rate than that accomplished during the past several years. With the advent of phase shift masks, the demands for technology development will be that much greater.

Among the areas of reticle manufacturing which must improve substantially to meet future requirements are: resist optimization, process automation and control, dry etching, feature linearity, submicron feature processing, reticle blanks and process chemistry. Additionally, the reticle manufacturer must identify, analyze, and reduce the component errors of process, equipment and raw materials.

This paper will review the evolution of reticle processing through the current state-of-the- art, and will assess the equipment, methodology, and materials required to extend reticle manufacture capabilities to the level required by 256Mb technology.

As leading edge semiconductor devices design rules continue their downward migration, the required reticle manufacturing tolerances continue tightening. In particular, as CD and registration specifications shrink, the metrology system's precision and accuracy used to measure reticle parameters becomes increasingly important. Additionally, as advanced reticle design tolerances tighten, the sample size needed to obtain the same level of confidence to be certain a given reticle meets specification also rises. Consequently, with shrinking tolerances and escalating sample sizes required to manufacture leading edge reticles, metrology is a key area requiring dramatic improvement in the 90's. A brief review of specification trends, metrology statistics, and the mask making equipment needed to meet such requirements is presented.

Reticles used in semiconductor lithography processes are required to be defect free. The meaning of the term "defect free" has evolved. This paper will provide a discussion on the evolution of this term and the defect inspection and repair equipment requirements for masks and reticles. A summary of current mask and reticle inspection and repair tools will also be provided.

The final step in the reticle manufacturing process takes place in the Cleaning and Pelliclization Area. Traditionally, this area covers reticle clean, pellicle mount, and particle inspection. Pellicles are used to protect the clean reticle: the pellicle membrane holds air borne particles away from the surface of the reticle, thus out of the focal plane, so the particles won't print on the wafer. The pellicle surface can tolerate larger particles than the reticle surface, making the reticle/pellicle combination more reliable in wafer fab.

In the past, the Cleaning and Pelliclization Area's main concern has been "soft" defects. Soft defects can be defined as any defect that can be removed by cleaning, such as particles, contamination, residue, stains, etc. The inspection tools used to verify the Cleaning and Pelliclization process have been focused on soft defect detection, i.e. particle inspection systems. Hard defects then, are defined as any defect involving the photomask substrate, such as missing or extra chrome, glass flaws, or scratches. The increased use of automation in the Cleaning and Pelliclization process forces concern and inspection for hard defects.

The only important specification in the Cleaning and Pelliclization process is zero defects, at a given size level. The given size level is complicated by the various locations of concern: the pellicle surfaces, the pattern side surfaces, and the glass side surfaces. As die sizes continue to increase, reticles have fewer dies. This places a tremendous responsibility on the Cleaning and Pelliclization area to deliver a reticle with zero printable killer defects, and zero defects that may move from a non-printing position into a printing position.

This paper will first cover defect definitions, locations, specifications, and the current status of the Cleaning and Pelliclization process in Production today, the process geared for 16-megabit DRAM specifications. The general process flow and the current trends in processing and equipment will be reviewed. Next, the process for the 64-megabit DRAM's, currently in development mode, will be discussed. Finally, the future projections for the needs in the Cleaning and Pelliclization Area to meet the challenges for the phase shift mask (PSM) and DUV technologies, and the 256-megabit DRAM process will be reviewed.

As the industry continues to move toward production in the 64- and 256-MB technology regime, the challenges posed by more stringent requirements associated with wafer lithography and reticle manufacturing are driving developments which may be out-pacing the ability of the industry to guarantee reticle performance.

The status of American competitiveness in high technology, and in particular the semiconductor industry, has been the subject of concern for some time now.¹ With the rise of Japanese manufactures to preeminence in the manufacturing of DRAM (Dynamic Random Access Memory) chips during the 1980's, the fundamental assumptions of modern economic theory have been called into question.² Various factors have been cited by various authors to account for the recent rise in Japanese competitiveness, including industrial policies of the Japanese government, differences in the cost of capital, investments in research and development, and the requirement of American companies to post financial results quarterly.³ There is, however, a real need for concrete case studies, which can examine the actual history of a technology and establish mechanisms of cause and effect.