This PDF file contains the front matter associated with SPIE Proceedings Volume 10145 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

The future of in-line process control is challenged by the incoming revolution of 3D architecture and complex integration schemes. CD and thin film metrology challenges being already covered [1], this paper will focus on overlay metrology challenge for in-line process control. . After an overview of the existing techniques, we will discuss the dominant errors, real and artificial. Then we will discuss of the importance of consistency vs accuracy. After few words about the importance of sampling, we will show that accuracy, if desirable, is not reachable to the last nanometer. To enable a good process control the efforts of our industry must remained focus on consistency of overlay metrology versus process effects.

Electrical test measurement in the back-end of line (BEOL) is crucial for wafer and die sorting as well as comparing intended process splits. Any in-line, nondestructive technique in the process flow to accurately predict these measurements can significantly improve mean-time-to-detect (MTTD) of defects and improve cycle times for yield and process learning. Measuring after BEOL metallization is commonly done for process control and learning, particularly with scatterometry (also called OCD (Optical Critical Dimension)), which can solve for multiple profile parameters such as metal line height or sidewall angle and does so within patterned regions. This gives scatterometry an advantage over inline microscopy-based techniques, which provide top-down information, since such techniques can be insensitive to sidewall variations hidden under the metal fill of the trench. But when faced with correlation to electrical test measurements that are specific to the BEOL processing, both techniques face the additional challenge of sampling. Microscopy-based techniques are sampling-limited by their small probe size, while scatterometry is traditionally limited (for microprocessors) to scribe targets that mimic device ground rules but are not necessarily designed to be electrically testable. A solution to this sampling challenge lies in a fast reference-based machine learning capability that allows for OCD measurement directly of the electrically-testable structures, even when they are not OCD-compatible. By incorporating such direct OCD measurements, correlation to, and therefore prediction of, resistance of BEOL electrical test structures is significantly improved. Improvements in prediction capability for multiple types of in-die electrically-testable device structures is demonstrated. To further improve the quality of the prediction of the electrical resistance measurements, hybrid metrology using the OCD measurements as well as X-ray metrology (XRF) is used. Hybrid metrology is the practice of combining information from multiple sources in order to enable or improve the measurement of one or more critical parameters. Here, the XRF measurements are used to detect subtle changes in barrier layer composition and thickness that can have second-order effects on the electrical resistance of the test structures. By accounting for such effects with the aid of the X-ray-based measurements, further improvement in the OCD correlation to electrical test measurements is achieved. Using both types of solution incorporation of fast reference-based machine learning on nonOCD-compatible test structures, and hybrid metrology combining OCD with XRF technology improvement in BEOL cycle time learning could be accomplished through improved prediction capability.

In this paper we discuss the edge placement error (EPE) for multi-patterning semiconductor manufacturing. In a multi-patterning scheme the creation of the final pattern is the result of a sequence of lithography and etching steps, and consequently the contour of the final pattern contains error sources of the different process steps. We describe the fidelity of the final pattern in terms of EPE, which is defined as the relative displacement of the edges of two features from their intended target position. We discuss our holistic patterning optimization approach to understand and minimize the EPE of the final pattern. As an experimental test vehicle we use the 7-nm logic device patterning process flow as developed by IMEC. This patterning process is based on Self-Aligned-Quadruple-Patterning (SAQP) using ArF lithography, combined with line cut exposures using EUV lithography. The computational metrology method to determine EPE is explained. It will be shown that ArF to EUV overlay, CDU from the individual process steps, and local CD and placement of the individual pattern features, are the important contributors. Based on the error budget, we developed an optimization strategy for each individual step and for the final pattern. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets.

Scaling of interconnect design rules in advanced nodes has been accompanied by a reducing metrology budget for BEOL process control. Traditional inline optical metrology measurements of BEOL processes rely on 1-dimensional (1D) film pads to characterize film thickness. Such pads are designed on the assumption that solid copper blocks from previous metallization layers prevent any light from penetrating through the copper, thus simplifying the effective film stack for the 1D optical model. However, the reduction of the copper thickness in each metallization layer and CMP dishing effects within the pad, have introduced undesired noise in the measurement. To resolve this challenge and to measure structures that are more representative of product, scatterometry has been proposed as an alternative measurement. Scatterometry is a diffraction based optical measurement technique using Rigorous Coupled Wave Analysis (RCWA), where light diffracted from a periodic structure is used to characterize the profile. Scatterometry measurements on 3D structures have been shown to demonstrate strong correlation to electrical resistance parameters for BEOL Etch and CMP processes. However, there is significant modeling complexity in such 3D scatterometry models, in particlar due to complexity of front-end-of-line (FEOL) and middle-of-line (MOL) structures. The accompanying measurement noise associated with such structures can contribute significant measurement error. To address the measurement noise of the 3D structures and the impact of incoming process variation, a hybrid scatterometry technique is proposed that utilizes key information from the structure to significantly reduce the measurement uncertainty of the scatterometry measurement. Hybrid metrology combines measurements from two or more metrology techniques to enable or improve the measurement of a critical parameter. In this work, the hybrid scatterometry technique is evaluated for 7nm and 14nm node BEOL measurements of interlayer dielectric (ILD) thickness, hard mask thickness and dielectric trench etch in complex 3D structures. The data obtained from the hybrid scatterometry technique demonstrates stable measurement precision, improved within wafer and wafer to wafer range, robustness in cases where 3D scatterometry measurements incur undesired shifts in the measurements, accuracy as compared to TEM and correlation to process deposition time. Process capability indicator comparisons also demonstrate improvement as compared to conventional scatterometry measurements. The results validate the suitability of the method for monitoring of production BEOL processes.

The development and integration of new materials and structures at the nanoscale require multiple parallel characterizations in order to control mostly physico-chemical properties as a function of applications. Among all properties, we can list physical properties such as: size, shape, specific surface area, aspect ratio, agglomeration/aggregation state, size distribution, surface morphology/topography, structure (including crystallinity and defect structure), solubility and chemical properties such as: structural formula/molecular structure, composition (including degree of purity, known impurities or additives), phase identity, surface chemistry (composition, charge, tension, reactive sites, physical structure, photocatalytic properties, zeta potential), hydrophilicity/lipophilicity. Depending on the final material formulation (aerosol, powder, nanostructuration…) and the industrial application (semiconductor, cosmetics, chemistry, automotive…), a fleet of complementary characterization equipments must be used in synergy for accurate process tuning and high production yield. The synergy between equipment so-called hybrid metrology consists in using the strength of each technique in order to reduce the global uncertainty for better and faster process control. The only way to succeed doing this exercise is to use data fusion methodology. In this paper, we will introduce the work that has been done to create the first generic hybrid metrology software platform dedicated to nanotechnologies process control. The first part will be dedicated to process flow modeling that is related to a fleet of metrology tools. The second part will introduce the concept of entity model which describes the various parameters that have to be extracted. The entity model is fed with data analysis as a function of the application (automatic analysis or semi-automated analysis). The final part will introduce two ways of doing data fusion on real data coming from imaging (SEM, TEM, AFM) and non-imaging techniques (SAXS). First approach is dedicated to high level fusion which is the art of combining various populations of results from homogeneous or heterogeneous tools, taking into account precision and repeatability of each of them to obtain a new more accurate result. The second approach is dedicated to deep level fusion which is the art of combining raw data from various tools in order to create a new raw data. We will introduce a new concept of virtual tool creator based on deep level fusion. As a conclusion we will discuss the implementation of hybrid metrology in semiconductor environment for advanced process control

Reducing overlay error via an accurate APC feedback system is one of the main challenges in high volume production of the current and future nodes in the semiconductor industry. The overlay feedback system directly affects the number of dies meeting overlay specification and the number of layers requiring dedicated exposure tools through the fabrication flow. Increasing the former number and reducing the latter number is beneficial for the overall efficiency and yield of the fabrication process. An overlay feedback system requires accurate determination of the overlay error, or fingerprint, on exposed wafers in order to determine corrections to be automatically and dynamically applied to the exposure of future wafers. Since current and future nodes require correction per exposure (CPE), the resolution of the overlay fingerprint must be high enough to accommodate CPE in the overlay feedback system, or overlay control module (OCM). Determining a high resolution fingerprint from measured data requires extremely dense overlay sampling that takes a significant amount of measurement time. For static corrections this is acceptable, but in an automated dynamic correction system this method creates extreme bottlenecks for the throughput of said system as new lots have to wait until the previous lot is measured. One solution is using a less dense overlay sampling scheme and employing computationally up-sampled data to a dense fingerprint. That method uses a global fingerprint model over the entire wafer; measured localized overlay errors are therefore not always represented in its up-sampled output. This paper will discuss a hybrid system shown in Fig. 1 that combines a computationally up-sampled fingerprint with the measured data to more accurately capture the actual fingerprint, including local overlay errors. Such a hybrid system is shown to result in reduced modelled residuals while determining the fingerprint, and better on-product overlay performance.

In this publication the authors have investigated both theoretically and experimentally the link between line edge roughness, target noise and overlay mark fidelity. Based on previous worki , a model is presented to explain how any given edge of a printed feature could have a mean position that varies stochastically (i.e., randomly, following a normal distribution) due to lithography stochastic variation. The amount of variation is a function of the magnitude of the LER (more accurately, all the statistical properties of the LER) and the length of the feature edge. These quantities have been analytically linked to provide an estimate for the minimum line length for both optical and e-beam based overlay metrology. The model results have been compared with experimental results from wafers manufactured at IMEC on both EUV and ArF lithographic processes developed for the 10 nm node, with extrapolation to the 5 nm node.

The optical coupling between gratings in diffraction-based overlay triggers a swing-curve^1,6 like response of the target’s signal contrast and overlay sensitivity through measurement wavelengths and polarizations. This means there are distinct measurement recipes (wavelength and polarization combinations) for a given target where signal contrast and overlay sensitivity are located at the optimal parts of the swing-curve that can provide accurate and robust measurements. Some of these optimal recipes can be the ideal choices of settings for production. The user has to stay away from the non-optimal recipe choices (that are located on the undesirable parts of the swing-curve) to avoid possibilities to make overlay measurement error that can be sometimes (depending on the amount of asymmetry and stack) in the order of several “nm”. To accurately identify these optimum operating areas of the swing-curve during an experimental setup, one needs to have full-flexibility in wavelength and polarization choices. In this technical publication, a diffraction-based overlay (DBO) measurement tool with many choices of wavelengths and polarizations is utilized on advanced production stacks to study swing-curves. Results show that depending on the stack and the presence of asymmetry, the swing behavior can significantly vary and a solid procedure is needed to identify a recipe during setup that is robust against variations in stack and grating asymmetry. An approach is discussed on how to use this knowledge of swing-curve to identify recipe that is not only accurate at setup, but also robust over the wafer, and wafer-to-wafer. KPIs are reported in run-time to ensure the quality / accuracy of the reading (basically acting as an error bar to overlay measurement).

Traditionally, the total measurement uncertainty (TMU) of overlay metrology focuses on dynamic precision, toolinduced-shift, and matching, while rarely examining inaccuracy. However, some researchers have recently shown that measurement inaccuracy can still be large despite optimized small TMU. Moreover, this inaccuracy can consume a significant portion of the overlay budget in the advanced nodes. In addition to qualifying the overlay error of inline wafers, overlay metrology is also used for improving on-product overlay as it provides corrective feedback to the lithography scanner. The accuracy of the correction terms as a result depends directly upon the measurement accuracy. As such, enhanced overlay accuracy will improve the overlay performance of reworked wafers, or subsequently exposed wafers. We have previously shown that a segmented Blossom target is more prone to asymmetry-induced inaccuracy than a nonsegmented target is [1]. Since target segmentation is inevitable for SADP and SAQP patterning processes, their resulting overlay performance leaves a lot to be desired. In our quest to reach for the true overlay, this paper reports our investigations on accuracy enhancement techniques for image-based targets, such as redundancy and self-calibration, and on the use of simulation-optimized scatterometry-based targets.

Technology shrinkage leads to tight specifications in advanced semiconductor industries. For several years’, metrology for lithography has been a key technology to address this challenge and to improve yield. More specifically overlay metrology is the object of special attention for tool suppliers and semiconductor manufacturers. This work focuses on Image Based Overlay (IBO) metrology for 28 nm FD-SOI CMOS front-end critical steps (gate and contact). With Overlay specifications below 10 nm, accuracy of the measurement is critical. In this study we show specific cases where target designs need to be optimized in order to minimize process effects (CMP, etch, deposition, etc.) that could lead to overlay measurement errors. Another important aspect of the metrology target is that its design must be device-like in order to better control and correct overlay errors leading to yield loss. Methodologies to optimize overlay metrology recipes are also presented. If the process effects cannot be removed entirely by target design optimization, recipe parameters have to be carefully chosen and controlled to minimize the influence of the target imperfection on measured overlay. With target asymmetry being one of the main contributors to those residual overlay measurement errors the Qmerit accuracy flag can be used to quantify the measurement error and recipe parameters can be set accordingly in order to minimize the target asymmetry impact. Reference technique measurements (CD-SEM) were used to check accuracy of the optimized overlay measurements.

Overlay control based on DI metrology of optical targets has been the primary basis for run-to-run process control for many years. In previous work we described a scenario where optical overlay metrology is performed on metrology targets on a high frequency basis including every lot (or most lots) at DI. SEM based FI metrology is performed ondevice in-die as-etched on an infrequent basis. Hybrid control schemes of this type have been in use for many process nodes. What is new is the relative size of the NZO as compared to the overlay spec, and the need to find more comprehensive solutions to characterize and control the size and variability of NZO at the 1x nm node: sampling, modeling, temporal frequency and control aspects, as well as trade-offs between SEM throughput and accuracy.

Overlay measurements are done for verification of the exposure and creation of process corrections for the next lots. As throughput of the overlay measurement tools is limited, it is desirable to avoid unnecessary measurements. Another concern can be that in-transparent stacks do not allow measuring a critical overlay relation directly. We developed methods for calculation of the overlay relation between two different layers between which there is no direct overlay measurement. We qualify the impact of sampling plans and the number of dependent layers. The indirect overlay calculation is applied on a significant high volume data set.

This paper will provide a high level overview of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry, concentrating on logic applications. First, we will take a broad view of the needs of patterned defect, critical dimensional (CD/3D), overlay and films metrology, and present the extensive list of applications for which metrology solutions are needed. Commonalities and differences among the various applications will be shown. We will then report on the gating technical limits of the most important of these metrology solutions to address the metrology challenges of future nodes, highlighting key metrology technology gaps requiring industry attention and investment

A methodology to evaluate the memory cell property of STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory) with a CD-SEM (Critical Dimension-Scanning Electron Microscope) was proposed. STTMRAM is one of the promising candidates among various emerging memories, owing to its low power consumption, low latency, and excellent endurance. Meanwhile, the major issues of STT-MRAM are its small resistance window and the etching-induced damage during memory pillar formation process. The resistance variability and the damage region should be minimized to achieve the reliable operation and the size scaling. The correlation analysis between the resistance and the physical dimension was performed. It provided quantitative information required for process development and control, such as the size-independent resistance variability, the width of the damaged region, and the origin of the short failures. They are essential for the investigation of the causes for the cell-to-cell resistance variability as well as for the quantification of the damage during etching process.

We introduce a set of designed tools for the analysis of lithography patterns and nano structures. The classical metrological analysis of these objects has the drawbacks of being time consuming, requiring manual tuning and lacking robustness and user friendliness. With the goal of improving the current situation, we propose new image processing tools at different levels: semi automatic, automatic and machine-learning enhanced tools. The complete set of tools has been integrated into a software platform designed to transform the lab into a virtual fab. The underlying idea is to master nano processes at the research and development level by accelerating the access to knowledge and hence speed up the implementation in product lines.

We summarize the metrology and inspection required for the development of nanoimprint lithography (NIL), which is recognized as a candidate for next-generation lithography. Template inspection and residual layer thickness (RLT) metrology are discussed. An optical-based inspection tool for replica template inspection showed sensitivity for defects below 10 nm with sufficient throughput. For the RLT control, in-die RLT metrology is needed. Because the metrology requires dense sampling, optical scatterometry is the best solution owing to its ability to measure profile features nondestructively with high throughput. For in-die metrology, we have developed a new hybrid metrology that can combine key information from these complex geometries with scatterometry measurements to reduce the impact on the RLT measurement due to the layers beneath the resist. The technologies discussed here will be important when NIL is applied for IC manufacturing, as well as in the development phases of those lithography technologies.

Realizing sensitive, high throughput and robust overlay measurement is a challenge in current 14nm and advanced upcoming nodes with transition to 300mm and upcoming 450mm semiconductor manufacturing, where slight deviation in overlay has significant impact on reliability and yield¹). Exponentially increasing number of critical masks in multi-patterning lithoetch, litho-etch (LELE) and subsequent LELELE semiconductor processes require even tighter overlay specification²). Here, we discuss limitations of current image- and diffraction- based overlay measurement techniques to meet these stringent processing requirements due to sensitivity, throughput and low contrast³). We demonstrate a new electrical measurement based technique where resistance is measured for a macro with intentional misalignment between two layers. Overlay is quantified by a parabolic fitting model to resistance where minima and inflection points are extracted to characterize overlay control and process window, respectively. Analyses using transmission electron microscopy show good correlation between actual overlay performance and overlay obtained from fitting. Additionally, excellent correlation of overlay from electrical measurements to existing image- and diffraction- based techniques is found. We also discuss challenges of integrating electrical measurement based approach in semiconductor manufacturing from Back End of Line (BEOL) perspective. Our findings open up a new pathway for accessing simultaneous overlay as well as process window and margins from a robust, high throughput and electrical measurement approach.

EUV lithography is promising for addressing upcoming, <10nm nodes for the semiconductor industry, but with this promise comes the need for reliable metrology techniques. In particular, there is a need for actinic mask inspection in which the imaging wavelength matches that of the intended lithography process, so that the most relevant defects are detected. Here, we demonstrate tabletop, ptychographic, coherent diffraction imaging (CDI) in reflection- and transmission-modes of extended samples, using a 13 nm high harmonic generation (HHG) source. We achieve the first sub-wavelength resolution EUV image (0.9λ) in transmission, the highest spatial resolution using any 13.5 nm source to date. We also present the first reflection-mode image obtained on a tabletop using 12.7 nm light. This work represents the first 12.7 nm reflection-mode image using any source of a general sample.

We introduce an extreme ultraviolet lithography (EUVL) mask defect review system (EMDRS) which has been developing in SAMUSNG. It applies a stand-alone high harmonic generation (HHG) EUV source as well as simple EUV optics consisting of a folding mirror and a zoneplate. The EMDRS has been continuously updated and utilized for various applications regarding defect printability in EUVL. One of the main roles of the EMDRS is to verify either mask repair or mask defect avoidance (MDA) by actinic reviews of defect images before and after the process. Using the MDA, small phase defects could be hidden below absorber patterns, but it is very challenging in case of layouts with high density patterns. The EMDRS clearly verify the success of the MDA while conventional SEM could not detect the images. In addition, we emulate images of the sub-resolution assist features (SRAFs) by the EMDRS and compared them with the wafer exposure results.

With extreme ultraviolet (EUV) lithography getting ready to enter high volume manufacturing, there is an imminent need to address EUV mask metrology infrastructure. Actinic defect inspection of patterned EUV photomasks has been identified as an essential step for mask qualification, but there is no commercial tool available right now. We address this gap with the RESCAN tool, a defect inspection platform being built at Paul Scherrer Institut (PSI), co-developed in collaboration with Nuflare Inc, Japan. RESCAN uses Scanning Scattering Contrast Microscopy (SSCM) and Scanning Coherent Diffraction Imaging (SCDI) for fast defect detection and fine defect localization. The development of a stand-alone tool based on these techniques relies on the availability of (1) a bright coherent EUV source with a small footprint and (2) a high frame-rate pixel detector with extended dynamic range and high quantum efficiency for EUV. We present two in-house projects at PSI addressing the development of these components: COSAMI and JUNGFRAU. COSAMI (COmpact Source for Actinic Mask Inspection), is a high-brightness EUV source optimized for EUV photons with a relatively small footprint. JUNGFRAU (adJUstiNg Gain detector FoR the Aramis User station) is a silicon-based hybrid pixel detector, developed in house at PSI and prototyped for EUV. With a high frame rate and dynamic range at 13.5 nm, this sensor solution is an ideal candidate for the RESCAN platform. We believe that these ongoing source and sensor programs will pave the way towards a comprehensive solution for actinic patterned mask inspection bridging the gap of actinic defect detection and identification on EUV reticles.

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

Non-linear overlay deformation is a well-known problem in critical lithography steps. A significant root cause is nonuniform stress, often caused by high temperature processes. Non-uniform stress in the wafer causes vertical deformation of the wafer, which can be measured by topography measurement equipment. In this case study, clustering is done on the topography data to sort each wafer into groups. Using the context information from the clustering, overlay feedback is computed on a wafer level basis. The evaluation of the approach is done with a run-to-run simulation, which allows optimization of this method and evaluation of the on-product overlay performance improvement. In the analysis, different wafer zones are distinguished to characterize the improvement potential for the different zones.

At SPIE 2013 in Metrology, Inspection, and Process Control for Microlithography an invited paper was published titled “In-line E-beam wafer metrology and defect inspection: the end of an era for image-based critical dimensional metrology? New life for defect inspection”. Three years have passed and numerous developments have occurred as predicted in this paper. The development of E-beam tools that can concurrently handle metrology and defect applications is one of the primary developments. In this paper, the capabilities of these new E-beam tools and their current use cases will be discussed in the areas of Critical Dimension Uniformity (CDU), In-die overlay, Hot spot and Physical defect inspection. Emphasis will be placed on use cases where “massive” CDU data is collected in order to increase yield learning for manufacturing (14nm) and decrease cycles of learning for development (7nm). Additionally, some of the other subject material from the previous publication will also be discussed such as the current state of E-beam critical dimension image fidelity and physical defect detection capabilities. Lastly, future directions and opportunities for In-line E-beam including Multi-beam and/or Multi-column E-beam will be discussed.

Engineers are continually faced with decisions about how much data they can collect. In this work, we present a statistically-based smart sampling methodology which can be used to target data collection and ensure that the risk to the product is clearly understood. Smart sampling combines knowledge of the distributions of control statistics with knowledge of the run length distributions they induce to balance the cost of information against the ability to respond to anomalies. We define and explore three characteristics that any sampling plan deemed “smart” must explicitly address: control errors that are associated with basing decisions on sample data, jeopardy that is associated with uncertainty about the true condition of the process, and the switching mechanism that controls the dynamic response to the latest information about the process. We show how the interplay of these characteristics can be exploited to comprehend the merits of a sampling plan. Practical examples of optical product inspection and process defectivity control are presented and explained.

In this paper we proposed a new semiconductor quality monitoring methodology – Process Sensor Log Analysis (PSLA) – using process sensor data for the detection of wafer defectivity and quality monitoring. We developed exclusive key parameter selection algorithm and user friendly system which is able to handle large amount of big data very effectively. Several production wafers were selected and analyzed based on the risk analysis of process driven defects, for example alignment quality of process layers. Thickness of spin-coated material can be measured using PSLA without conventional metrology process. In addition, chip yield impact was verified by matching key parameter changes with electrical die sort (EDS) fail maps at the end of the production step. From this work, we were able to determine that process robustness and product yields could be improved by monitoring the key factors in the process big data.

After critical lithography steps, overlay and CD are measured to determine if the wafers need to be re-worked. Traditionally, overlay metrics are applied per X/Y-direction and, a CD metric is computed independently. From design standpoint, electrical failure is based on a complex interaction between CD deviations and overlay errors. We propose a method including design constraints, where results of different measurement steps are not judged individually, but in a combined way. We illustrate this with a critical design feature consisting of a contact requiring minimum distance to a neighboring metal line, resulting in much better correlation to yield than traditional methods.

With photolithography as the fundamental patterning step in the modern nanofabrication process, every wafer within a semiconductor fab will pass through a lithographic apparatus multiple times. With more than 20,000 sensors producing more than 700GB of data per day across multiple subsystems, the combination of a light source and lithographic apparatus provide a massive amount of information for data analytics. This paper outlines how data analysis tools and techniques that extend insight into data that traditionally had been considered unmanageably large, known as adaptive analytics, can be used to show how data collected before the wafer is exposed can be used to detect small process dependent wafer-towafer changes in overlay.

Surface topography on post-CMP processing can be measured with white light interference microscopy to determine the planarity. Results are used to avoid under or over polishing and to decrease dishing. The numerical output of the surface topography is the RMS (root-mean-square) of the height. Beyond RMS, the topography image is visually examined and not further quantified. Subjective comparisons of the height maps are used to determine optimum CMP process conditions. While visual comparison of height maps can determine excursions, it’s only through manual inspection of the images. In this work we describe methods of quantifying post-CMP surface topography characteristics that are used in other technical fields such as geography and facial-recognition. The topography image is divided into small surface patches of 7x7 pixels. Each surface patch is fitted to an analytic surface equation, in this case a third order polynomial, from which the gradient, directional derivatives, and other characteristics are calculated. Based on the characteristics, the surface patch is labeled as peak, ridge, flat, saddle, ravine, pit or hillside. The number of each label and thus the associated histogram is then used as a quantified characteristic of the surface topography, and could be used as a parameter for SPC (statistical process control) charting. In addition, the gradient for each surface patch is calculated, so the average, maximum, and other characteristics of the gradient distribution can be used for SPC. Repeatability measurements indicate high confidence where individual labels can be lower than 2% relative standard deviation. When the histogram is considered, an associated chi-squared value can be defined from which to compare other measurements. The chi-squared value of the histogram is a very sensitive and quantifiable parameter to determine the within wafer and wafer-to-wafer topography non-uniformity. As for the gradient histogram distribution, the chi-squared could again be calculated and used as yet another quantifiable parameter for SPC. In this work we measured the post Cu CMP of a die designed for 14nm technology. A region of interest (ROI) known to be indicative of the CMP processing is chosen for the topography analysis. The ROI, of size 1800 x 2500 pixels where each pixel represents 2um, was repeatably measured. We show the sensitivity based on measurements and the comparison between center and edge die measurements. The topography measurements and surface patch analysis were applied to hundreds of images representing the periodic process qualification runs required to control and verify CMP performance and tool matching. The analysis is shown to be sensitive to process conditions that vary in polishing time, type of slurry, CMP tool manufacturer, and CMP pad lifetime. Keywords: Keywords: CMP, Topography, Image Processing, Metrology, Interference microscopy, surface processing [1] De Lega, Xavier Colonna, and Peter De Groot. "Optical topography measurement of patterned wafers." Characterization and Metrology for ULSI Technology 2005 788 (2005): 432-436. [2] de Groot, Peter. "Coherence scanning interferometry." Optical Measurement of Surface Topography. Springer Berlin Heidelberg, 2011. 187-208. [3] Watson, Layne T., Thomas J. Laffey, and Robert M. Haralick. "Topographic classification of digital image intensity surfaces using generalized splines and the discrete cosine transformation." Computer Vision, Graphics, and Image Processing 29.2 (1985): 143-167. [4] Wang, Jun, et al. "3D facial expression recognition based on primitive surface feature distribution." Computer Vision and Pattern Recognition, 2006 IEEE Computer Society Conference on. Vol. 2. IEEE, 2006.

At 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical to prevent hotspots from becoming yield-limiting defects. We previously established proof of concept for a systematic approach to identify the most critical pattern locations, i.e. hotspots, in a reticle layout by computational lithography and combining process window characteristics of these patterns with across-wafer process variation data to predict where hotspots may become yield impacting defects [1,2]. The current paper establishes the impact of micro-topography on a 28nm metal layer, and its correlation with hotspot best focus variations across a production chip layout. Detailed topography measurements are obtained from an offline tool, and pattern-dependent best focus (BF) shifts are determined from litho simulations that include mask-3D effects. We also establish hotspot metrology and defect verification by SEM image contour extraction and contour analysis. This enables detection of catastrophic defects as well as quantitative characterization of pattern variability, i.e. local and global CD uniformity, across a wafer to establish hotspot defect and variability maps. Finally, we combine defect prediction and verification capabilities for process monitoring by on-product, guided hotspot metrology, i.e. with sampling locations being determined from the defect prediction model and achieved prediction accuracy (capture rate) around 75%

Line edge placement error is a limiting factor in multipatterning schemes which are required for advanced nodes in high volume manufacturing for the semiconductor industry. Thus, we aim to develop an approach which provides both a quantitative estimate of whether a segment of a feature edge is in the ideal location and a quantitative estimate of the long wavelength roughness. The method is described, numerical simulation models its application to the issue of distortion caused by SEM aberrations, and the method is applied to a sample data set of SEM images. We show that the method gives a robust estimate of a major component leading to feature edge placement error. Long wavelength distortions either from SEM aberrations or from long wavelength noise have a clear statistical signature. This methodology applied to a large, consistently acquired SEM data set allows estimates as to important elements required to assess the line edge placement error issue and to whether there is underlying long wavelength roughness which arises from physical sources

Stochastic-induced roughness of lithographic features continues to be of great concern due to its impact on semiconductor devices. In particular, rare events (large deviations in edge positions due to roughness) can cause catastrophic failure of a chip, but are hard to predict. Here, a new methodology, the level crossing method, is used to characterize the statistical behavior of edge roughness with the goal of predicting extreme events. Using experimental results from EUV lithography, the distribution of edge deviations was found to have tails significantly heavier than a normal distribution. While further work is required, these heavy tails could prove problematic when EUV is used in high volume manufacturing.

Line-edge roughness (LER) has important impacts on the quality of semiconductor device performance, and power spectrum estimates are useful tools in characterizing it. These estimates are often obtained by taking measurements of many lines and averaging a classical power spectrum estimate from each one. While this approach improves the variance of the estimate there are disadvantages to the collection of many measurements with current microscopy techniques. We propose techniques with widespread application in other fields which simultaneously reduce data requirements and variance of LER power spectrum estimates over current approaches at the price of computational complexity. Multitaper spectral analysis uses an orthogonal collection of data windowing functions or tapers on a set of data to obtain a set of approximately statistically independent spectrum estimates. The Welch overlapped segment averaging spectrum estimate is an earlier approach to reusing data. There are known techniques to calculate error bars for these families of spectrum estimators, and we experiment with random rough lines simulated by Mack’s technique based on the Thorsos method.

Metrology of nanoscale patterns poses multiple challenges that range from measurement noise, metrology errors, probe size etc. Optical Metrology has gained a lot of significance in the semiconductor industry due to its fast turn around and reliable accuracy, particularly to monitor in-line process variations. Apart from monitoring critical dimension, thickness of films, there are multiple parameters that can be extracted from Optical Metrology models3. Sidewall angles, material compositions etc., can also be modeled to acceptable accuracy. Line edge and Line Width roughness are much sought of metrology following critical dimension and its uniformity, although there has not been much development in them with optical metrology. Scanning Electron Microscopy is still used as a standard metrology technique for assessment of Line Edge and Line Width roughness. In this work we present an assessment of Optical Metrology and its ability to model roughness from a set of structures with intentional jogs to simulate both Line edge and Line width roughness at multiple amplitudes and frequencies. We also present multiple models to represent roughness and extract relevant parameters from Optical metrology. Another critical aspect of optical metrology setup is correlation of measurement to a complementary technique to calibrate models. In this work, we also present comparison of roughness parameters extracted and measured with variation of image processing conditions on a commercially available CD-SEM tool.

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

SEM images provide valuable information about patterning capability. Geometrical properties such as Critical Dimension (CD) can be extracted from them and are used to calibrate OPC models, thus making OPC more robust and reliable. However, there is currently a shortage of appropriate metrology tools to inspect complex two-dimensional patterns in the same way as one would work with simple one-dimensional patterns. In this article we present a full framework for the analysis of SEM images. It has been proven to be fast, reliable and robust for every type of structure, and particularly for two-dimensional structures. To achieve this result, several innovative solutions have been developed and will be presented in the following pages. Firstly, we will present a new noise filter which is used to reduce noise on SEM images, followed by an efficient topography identifier, and finally we will describe the use of a topological skeleton as a measurement tool that can extend CD measurements on all kinds of patterns.

Today’s CD-SEM metrology is challenged when it comes to measuring complex features found in patterning hotspots (like tip to tip, tip to side, necking and bridging). Metrology analysis tools allow us to extract SEM contours of a feature and convert them into a GDS format from which dimensional data can be extracted. While the CD-SEM is being used to take images, the actual measurement and the choice of what needs to be measured is done offline. Most of the time this method is used for OPC model creation but barely for process variability analysis at nominal process conditions. We showed in a previous paper [1] that it is possible to study lithography to etch transfer behavior of a hotspot using SEM contours. The goal of the current paper is to go extend this methodology to quantify process variability of 2D features using a new tooling to measure contour data.

Given the potential impact of distortions within the Field Of View (FOV) of the SEM, we need a method to quantify and describe them. We will show a method to find the magnitude and directions of the distortions. This description will enable assessment of impact on local distance measurements like edge placement errors (EPE) analysis and contour measurements. Knowing the distortions with sufficient resolution and stability can also enable corrections for this phenomenon. We will show that applying this correction in post processing, we can bring back the absolute measurement error from 1.5 nm to 0.3 nm.

Qualitative comparisons have been made in the literature between the scattering off deep-subwavelength-sized defects and the scattering off spheres in free space to illustrate the challenges of optical defect inspection with decreasing patterning sizes. The intensity scattered by such a sphere (for diameters sized well below the wavelength) is proportional to its diameter to the sixth power, but also scales inversely to the fourth power of the wavelength. This paper addresses through simulation the potential advantages of applying shorter wavelengths for improved patterned defect inspection. Rigorous finite-difference time-domain 3-D electromagnetic modeling of the scattering from patterned defect layouts has been performed at five wavelengths which span the deep ultraviolet (193 nm), the vacuum ultraviolet (157 nm and 122 nm), and the extreme ultraviolet (47 nm and 13 nm). These patterned structures and defects are based upon publicly disclosed geometrical cross-sectional information from recent manufacturing processes, which then have been scaled down to an 8 nm Si linewidth. Simulations are performed under an assumption that these wavelengths have the same source intensity, noise sources, and optical configuration, but wavelengthdependent optical constants are considered, thus yielding a more fundamental comparison of the potential gains from wavelength scaling. To make these results more practical, future work should include simulations with more process stacks and with more materials as well as the incorporation of available source strengths, known microscope configurations, and detector quantum efficiencies. In this study, a 47 nm wavelength yielded enhancements in the signal-to-noise by a factor of five compared to longer wavelengths and in the differential intensities by as much as three orders-of-magnitude compared to 13 nm, the actinic wavelength for EUV semiconductor manufacturing.

General approaches to realize higher sensitivity in optical inspection system are using shorter wavelength including UV and higher NA for objective lens. Extreme performances of imaging and illumination systems in a situation of wellmatched to each other are inevitable for the further effort on an effective optical detection of fine defects in patterned wafer. This study focused on the dark field illumination systems satisfying hi areal uniformity and concentration efficiency for the specific conditions of non-symmetric illumination area and critical slanted angle. Three different types of anamorphic dark field illumination systems namely, Far-field Areal Illumination (FAI), Near-field Areal Illumination (NAI) and Farfield Linear Illumination (FLI), are designed and evaluated by brightness, uniformity and concentration efficiency of beam intensity.

The semiconductor industry is moving toward a half-pitch of 7 nm. The required metrology equipment should be one order of magnitude more accurate than that. Any metrology tool is only as good as it is calibrated. The characterization of metrology systems requires test patterns that are one order of magnitude smaller than the measured features. The test sample was designed in such a way that the distribution of linewidths appears to be random at any location and any magnification. The power spectral density of such pseudo-random test pattern is inherently flat, down to the minimum size of lines. Metrology systems add a cut-off of the spectra at high frequencies; the shape of the cut-off characterizes the system in its entire dynamic range. This method is widely used in optics, and has allowed optical systems to be perfected down to their diffraction limit. There were attempts to use the spectral method to characterize nanometrology systems such as SEMs, but the absence of natural samples with known spatial frequencies was a common problem. Pseudo-random test patterns with linewidths down to 1.5 nm were fabricated. The system characterization includes the imaging of a pseudo-random test sample and image analysis by a developed software to automatically extract the power spectral density and the contrast transfer function of the nanoimaging system.

The availability of metrology solutions, one of the key factors to drive leading edge semiconductor devices and processes, can be confronted with difficulties in the advanced node. For developing new metrology solutions, high quality test structures fabricated at specific sizes are needed. Conventional resist-based lithography have been utilized to manufacture such samples. However, it can encounter significant resolution difficulties or requiring complicated optimization process for advanced technology node. In this work, potential of helium ion beam direct milling (HIBDM) for fabricating metrology test structures with programmed imperfection is investigated. Features down to 5 nm are resolvable without implementing any optimization method. Preliminary results have demonstrated that HIBDM can be a promising alternative to fabricate metrology test structures for advanced metrology solutions in sub 10 nm node.

A novel method of sub-nanometer uncertainty for the 3D-profile measurement and LWR (Line Width Roughness) measurement by using FIB (Focused Ion Beam) processing, and TEM (Transmission Electron Microscope) and CD-SEM (Critical Dimension Scanning Electron Microscope) images measurement is proposed to standardize 3D-profile measurement through reference metrology. In this article, we apply the methodology to line profile measurements and roughness measurement of advanced FinFET (Fin-shaped Field-Effect Transistor) features. The FinFET features are horizontally sliced as a thin specimen by FIB micro sampling system. Horizontally images of the specimens are obtained then by a planar TEM. LWR is calculated from the edges positions on TEM images. Moreover, we already have demonstrated the novel on-wafer 3D-profile metrology as "FIB-to-CDSEM method" with FIB slope cut and CD-SEM measuring. Using the method, a few micrometers wide on a wafer is coated and cut by 45-degree slope using FIB tool. Then, the wafer is transferred to CD-SEM to measure the cross section image by top down CD-SEM measurement. We applied FIB-to-CDSEM method to a CMOS image sensor feature. The 45-degree slope cut surface is observed using AFM. The surface profile of slope cut surface and line profiles are analyzed for improving the accuracy of FIB-to-CDSEM method.

The logic manufacturing process requires small in-device metrology targets to exploit the full dose correction potential of the modern scanners and process tools. A high-NA angular resolved scatterometer (YieldStar S-1250D) was modified to demonstrate the possibility of OCD measurements on 5x5µm2 targets. The results obtained on test wafers in a logic manufacturing environment, measured after litho and after core etch, showed a good correlation to larger reference targets and AEI to ADI intra-field CDU correlation, thereby demonstrating the feasibility of OCD on such small targets. The data was used to determine a reduction potential of 55% for the intra-field CD variation, using 145 points per field on a few inner fields, and 33% of the process induced across wafer CD variation using 16 points per field full wafer. In addition, the OCD measurements reveal valuable information on wafer-to-wafer layer height variations within a lot.

Device scaling has not only driven the use of measurements on more complex structures, in terms of geometry, materials, and tighter ground rules, but also the need to move away from non-patterned measurement sites to patterned ones. This is especially of concern for very thin film layers that have a high thickness dependence on structure geometry or wafer pattern factor. Although 2-dimensional (2D) sites are often found to be sufficient for process monitoring and control of very thin films, sometimes 3D sites are required to further simulate structures within the device. The measurement of film thicknesses only a few atoms thick on complex 3D sites, however, are very challenging. Apart from measuring thin films on 3D sites, there is also a critical need to measure parameters on 3D sites, which are weak and less sensitive for OCD (Optical Critical Dimension) metrology, with high accuracy and precision. Thus, state-ofthe-art methods are needed to address such metrology challenges. This work introduces the concept of Enhanced OCD which uses various methods to improve the sensitivity and reduce correlations for weak parameters in a complex measurement. This work also describes how more channels of information, when used correctly, can improve the precision and accuracy of weak, non-sensitive or complex parameters of interest.

In this paper we propose a “film on grating” (FoG) measurement technique using spectroscopic ellipsometry (SE) that can enable sub-Ångstrom level precision for multi-layer film thickness measurement on topographies that closely approximate the device structure. FoG follows the industry trends to 'measure what matters' and provides thickness measurement data from patterned structures that has much stronger correlation to actual device performance. We also explore the impact of deviations in the film stack that can appreciably alter the device performance. One of the key device performance metrics that we will investigate is the leakage current, which is highly sensitive to process variations or defectivity. Measuring both the thickness and the bandgap of the HK dielectric permits excellent correlation with leakage current as determined by electrical testing of the device. The ability to predict electrical parameters effectively will greatly accelerate learning cycles during process development and can enable real time product control on existing inline metrology tools.

Optical 3-D nanostructure metrology utilizes a model-based metrology approach to determine critical dimensions (CDs) that are well below the inspection wavelength. Our project at the National Institute of Standards and Technology is evaluating how to attain key CD and shape parameters from engineered in-die capable metrology targets. More specifically, the CDs are determined by varying the input parameters for a physical model until the simulations agree with the actual measurements within acceptable error bounds. As in most applications, establishing a reasonable balance between model accuracy and time efficiency is a complicated task. A well-established simplification is to model the intrinsically finite 3-D nanostructures as either periodic or infinite in one direction, reducing the computationally expensive 3-D simulations to usually less complex 2-D problems. Systematic errors caused by this simplified model directly influence the fitting of the model to the measurement data and are expected to become more apparent with decreasing lengths of the structures. In this paper we investigate these effects, and will report experimental set-ups, e.g., the used illumination numerical apertures and focal ranges, that can increase the validity of the 2-D approach.

The evaluation of scatterometry for monitoring intended variations in innovative scatterometry targets that mimic nonuniformities potentially caused by multibeam Maskless Lithography (MEB-ML2) is presented. Specialized scatterometry targets consisting of lines and spaces were produced that have portions exposed using the nominal, or POR (Process of Record), dose, and portions exposed with a slightly different dose. These exposure plans created targets with different line CDs (critical dimensions). Multiple target designs were implement, each with a different combination of magnitude of CD shift and size of the region containing lines with a shifted CD. The scatterometry, or OCD (Optical Critical Dimension), spectra show clear shifts caused by the regions with shifted CD, and trends of the scatterometry results match well with trends of the estimated CD as well as the trends produced by measurements using a critical dimension scanning electron microscope (CD-SEM) system. Finally, the OCD results are correlated to the CD-SEM measurements. Taking into account resist morphology variations across the wafer, correlations between OCD and CD-SEM of the weighted average CD across the various targets are shown to be very good. Correlations are done using the rigorous TMU analysis methodology. Due to the different targeted CD values within each scatterometry structure, a new methodology for estimating the error of the CD-SEM measurements for nominally non-uniform targets is presented.

The majority of scatterometric production control models assume constant optical properties of the materials and only dimensional parameters are allowed to vary. However, this assumption, especially in case of thin-metal films, negatively impacts model precision and accuracy. In this work we focus on optical modeling of the TiN metal hardmask for scatterometry applications. Since the dielectric function of TiN exhibits thickness dependence, we had to take this fact into account. Moreover, presence of the highly absorbing films influences extracted thicknesses of dielectric layers underneath the metal films. The later phenomenon is often not reflected by goodness of fit. We show that accurate optical modeling of metal is essential to achieve desired scatterometric model quality for automatic process control in microelectronic production. Presented modeling methodology can be applied to other TiN applications such as diffusion barriers and metal gates as well as for other metals used in microelectronic manufacturing for all technology nodes.

The semiconductor industry continues to drive patterning solutions that enable devices with higher memory storage capacity, faster computing performance, and lower cost per transistor. These developments in the field of semiconductor manufacturing along with the overall minimization of the size of transistors require continuous development of metrology tools used for characterization of these complex 3D device architectures. Optical scatterometry or optical critical dimension (OCD) is one of the most prevalent inline metrology techniques in semiconductor manufacturing because it is a quick, precise and non-destructive metrology technique. However, at present OCD is predominantly used to measure the feature dimensions such as line-width, height, side-wall angle, etc. of the patterned nano structures. Use of optical scatterometry for characterizing defects such as pitch-walking, overlay, line edge roughness, etc. is fairly limited. Inspection of process induced abnormalities is a fundamental part of process yield improvement. It provides process engineers with important information about process errors, and consequently helps optimize materials and process parameters. Scatterometry is an averaging technique and extending it to measure the position of local process induced defectivity and feature-to-feature variation is extremely challenging. This report is an overview of applications and benefits of using optical scatterometry for characterizing defects such as pitch-walking, overlay and fin bending for advanced technology nodes beyond 7nm. Currently, the optical scatterometry is based on conventional spectroscopic ellipsometry and spectroscopic reflectometry measurements, but generalized ellipsometry or Mueller matrix spectroscopic ellipsometry data provides important, additional information about complex structures that exhibit anisotropy and depolarization effects. In addition the symmetry-antisymmetry properties associated with Mueller matrix (MM) elements provide an excellent means of measuring asymmetry present in the structure. The useful additional information as well as symmetry-antisymmetry properties of MM elements is used to characterize fin bending, overlay defects and design improvements in the OCD test structures are used to boost OCDs’ sensitivity to pitch-walking. In addition, the validity of the OCD based results is established by comparing the results to the top down critical dimensionscanning electron microscope (CD-SEM) and cross-sectional transmission electron microscope (TEM) images.

Monte Carlo-based SEM image simulation can reproduce SEM micrographs by calculating scattering events of primary electrons inside the target materials. By using the simulated SEM images, it is possible to optimize imaging conditions prior to the specimen observation, which could save time for finding suitable observation condition. However, a recent trend of miniaturized and 3-dimentional structures of semiconductor devices, and introduction of various novel materials have created a challenge for such SEM image simulation techniques; that is, more precise and accurate modeling is required. In this paper, we present a quantitatively accurate BSE simulation and a precise parameters setting in voltage contrast simulation, for both to reproduce experimental SEM images accurately. We apply these simulation techniques to optimize the accelerating voltage of SEM for sub-surface imaging, and to analyze a charge distribution on the insulating specimen under the electron irradiation. These applications promise the advancement in developing a new device by preparing inspecting condition in a timely manner.

The miniaturization of semiconductors continues, importance of overlay measurement is increasing. We measured overlay with analysis SEM called Miracle Eye which can output ultrahigh acceleration voltage in 1998. Meanwhile, since 2006, we have been working on SEM based overlay measurement and developed overlay measurement function of the same layer using CD-SEM. Then, we evaluated overlay of the same layer pattern after etching. This time, in order to measure overlay after lithography, we evaluated the see-through overlay using high voltage SEM CV5000 released in October 2016. In collaboration between imec and Hitachi High-Technologies, we evaluated repeatability, TIS of SEM-OVL as well as correlation between SEM-OVL and Opt-OVL in the M1@ADI and V0@ADI process. Repeatability and TIS results are reasonable and SEM-OVL has good correlation with Opt-OVL. By overlay measurement using CV 5000, we got the following conclusions. (1)SEM_OVL results of both M1 and V0 at ADI show good correlation to OPT_OVL. (2)High voltage SEM can prove the measurement capability of a small pattern(Less than 1~2um) like device that can be placed in-die area. (3)"In-die SEM based overlay" shows possibility for high order control of scanner

Voltage contrast (VC) images obtained using an energy filter (EF) were used to measure the bottom surface of high-aspect- ratio (HAR) structures. The VC images obtained using the conventional EF were sensitive to variations in wafer potential. Since CD-SEM metrology requires precise EF voltage control when using VC images, we developed an EF voltage correction method to be used at each measurement point. Consequently, bottom-edge measurement, independent of the wafer potential fluctuations, was achieved by using the newly developed EF. Our developed technique is effective for CD-SEM metrology using VC images.

In recent trend of semiconductor manufacturing, accurate critical dimension (CD) metrology is required to realize miniaturized three-dimensional (3D) structures. However, the conventional edge contrast of scanning electron microscopy (SEM) is often suppressed when imaging the deep bottom of the 3D structures. In this paper, we propose effective approaches realizing the improved SEM image contrast for such metrology targets. Our approach utilizes the principle of the SEM contrast, and optimizes the three major influencing factors of SEM contrast; signal generation, signal propagation inside the specimen, and signal detection by the detectors. We show the examples of improved image contrast including, embedded voids imaging by high landing beam energy, contact-hole bottom imaging by angular selective detections, and precise edge position extraction realized by energy-angular selective imaging.

Sidewall image transfer has become a key enabler of future design shrink. It is consisted of several process steps that multiply the number of lithography backbone patterns in a self-aligned form, shrinking pattern and pitch sizes. The quality of the image transfer process depends on the characteristics of the sidewall pattern morphology. Rectangular Sidewalls with a flat top and vertical edges will result with symmetrical and uniform etched image. On the other hand, Facet top, bent sidewalls, sloped edges or foot, may distort the etched image. In this paper we present a description of the 3DSEM metrology technique used, simulation results, and demonstrate three dimensional characterization of Sidewalls pattern fabricated with different etch recipes: Top Facet measurements vs cross section images; Edge slop and foot characterization

When design rule is mitigating to smaller dimension, process variation requirement is tighter than ever and challenges the limits of device yield. Masks, lithography, etching and other processes have to meet very tight specifications in order to keep defect and CD within the margins of the process window. Conventionally, Inspection and metrology equipments are utilized to monitor and control wafer quality in-line. In high throughput optical inspection, nuisance and review-classification become a tedious labor intensive job in manufacturing. Certain high-resolution SEM images are taken to validate defects after optical inspection. These high resolution SEM images catch not only optical inspection highlighted point, also its surrounding patterns. However, this pattern information is not well utilized in conventional quality control method. Using this complementary design based pattern monitor not only monitors and analyzes the variation of patterns sensitivity but also reduce nuisance and highlight defective patterns or killer defects. After grouping in either single or multiple layers, systematic defects can be identified quickly in this flow. In this paper, we applied design based pattern monitor in different layers to monitor process variation impacts on all kinds of patterns. First, the contour of high resolutions SEM image is extracted and aligned to design with offset adjustment and fine alignment [1]. Second, specified pattern rules can be applied on design clip area, the same size as SEM image, and form POI (pattern of interest) areas. Third, the discrepancy of contour and design measurement at different pattern types in measurement blocks. Fourth, defective patterns are reported by discrepancy detection criteria and pattern grouping [4]. Meanwhile, reported pattern defects are ranked by number and severity by discrepancy. In this step, process sensitive high repeatable systematic defects can be identified quickly Through this design based process pattern monitor method, most of optical inspection nuisances can be filtered out at contour to design discrepancy measurement. Daily analysis results are stored at database as reference to compare with incoming data. Defective pattern library contains existing and known systematic defect patterns which help to catch and identify new pattern defects or process impacts. On the other hand, this defect pattern library provides extra valuable information for mask, pattern and defects verification, inspection care area generation, further OPC fix and process enhancement and investigation.

As critical dimensions for advanced two dimensional (2D) DUV patterning continue to shrink, the exact process window becomes increasingly difficult to determine. The defect size criteria shrink with the patterning critical dimensions and are well below the resolution of current optical inspection tools. As a result, it is more challenging for traditional bright field inspection tools to accurately discover the hotspots that define the process window. In this study, we use a novel computational inspection method to identify the depth-of-focus limiting features of a 10 nm node mask with 2D metal structures (single exposure) and compare the results to those obtained with a traditional process windows qualification (PWQ) method based on utilizing a focus modulated wafer and bright field inspection (BFI) to detect hotspot defects. The method is extended to litho-etch litho-etch (LELE) on a different test vehicle to show that overlay related bridging hotspots also can be identified.

In the course of assessing OPC compact modeling capabilities and future requirements, we chose to investigate the interface between CD-SEM metrology methods and OPC modeling in some detail. Two linked observations motivated our study: 1) OPC modeling is, in principle, agnostic of metrology methods and best practice implementation. 2) Metrology teams across the industry use a wide variety of equipment, hardware settings, and image/data analysis methods to generate the large volumes of CD-SEM measurement data that are required for OPC in advanced technology nodes. Initial analyses led to the conclusion that many independent best practice metrology choices based on systematic study as well as accumulated institutional knowledge and experience can be reasonably made. Furthermore, these choices can result in substantial variations in measurement of otherwise identical model calibration and verification patterns. We will describe several experimental 2D test cases (i.e., metal, via/cut layers) that examine how systematic changes in metrology practice impact both the metrology data itself and the resulting full chip compact model behavior. Assessment of specific methodology choices will include: • CD-SEM hardware configurations and settings: these may range from SEM beam conditions (voltage, current, etc.,) to magnification, to frame integration optimizations that balance signal-to-noise vs. resist damage. • Image and measurement optimization: these may include choice of smoothing filters for noise suppression, threshold settings, etc. • Pattern measurement methodologies: these may include sampling strategies, CD- and contour- based approaches, and various strategies to optimize the measurement of complex 2D shapes. In addition, we will present conceptual frameworks and experimental methods that allow practitioners of OPC metrology to assess impacts of metrology best practice choices on model behavior. Finally, we will also assess requirements posed by node scaling on OPC model accuracy, and evaluate potential consequences for CD-SEM metrology capabilities and practices.

Measurement of feature roughness is complicated by the confounding noise inherent in SEM images. Edge detection typically requires image filtering to be reliable, but such filtering inevitably alters the roughness that one is trying to measure. Thus, there is a need for an edge detection approach that reliably detects edges in very noisy SEM images without the use of image filtering. The analytical linescan model (ALM) accomplishes this goal by using a physical model for linescan generation to constrain the possible shape of a linescan. Inverting a calibrated model allows edge positions to be estimated with very low sensitivity to noise. The ALM was used to detect edges for the application of roughness measurements and shown to provide superior results compared to conventional methods that employ image filtering.

We use the ZEISS MultiSEM to inspect patterns on separated chips of a semiconductor wafer suited for process window characterization at imec-N10 logic node. We systematically analyze the impact of imaging parameters of the MultiSEM on quantitative metrics extracted from the images, e.g., CD repeatability and relative defect capture, and demonstrate that the MultiSEM is able to image the wafer patterns, track their variations through the process conditions of the lithography scanner, and consistently find patterning defects limiting the lithographic process window.

The introduction of finFET has contributed tremendously in making scaling beyond 20nm a reality. However, the complexity of these 3D high performance transistors generate inherent new defects that are difficult to detect and this heightens concerns over device quality and reliability at future technology nodes. New methods and approaches are thus needed to effectively detect and monitor this new class of defects. Color imaging in Scanning Electron Microscopy (SEM) is not a new phenomenon. However, its use in inline SEM based defect review in the semiconductor industry is relatively new. In this work SEM color imaging is used to enhance SEM review redetection of a buried defect, Gate to Source/Drain short in 14nm finFET device. Defect sites on the wafer are flagged as defect events by Bright Field (BF) defect inspection tools. The review tool uses SEM optics to redetect the defect event using a combination of very high electron landing energies in excess of 5 keV and high beam current of about 3,000 pA to confirm the existence of the defect. The defect signal is further processed through a color coder by the SEM review equipment to create a “false” color image to enhance defect redetection and help to accurately classify defect.

Multi-channel gate all around (GAA) semiconductor devices march closer to becoming a reality in production as their maturity in development continues. From this development, an understanding of what physical parameters affecting the device has emerged. The importance of material property characterization relative to that of other physical parameters has continued to increase for GAA architecture when compared to its relative importance in earlier architectures. Among these materials properties are the concentration of Ge in SiGe channels and the strain in these channels and related films. But because these properties can be altered by many different process steps, each one adding its own variation to these parameters, their characterization and control at multiple steps in the process flow is crucial. This paper investigates the characterization of strain and Ge concentration, and the relationships between these properties, in the PFET SiGe channel material at the earliest stages of processing for GAA devices. Grown on a bulk Si substrate, multiple pairs of thin SiGe/Si layers that eventually form the basis of the PFET channel are measured and characterized in this study. Multiple measurement techniques are used to measure the material properties. In-line X-Ray Photoelectron Spectroscopy (XPS) and Low Energy X-Ray Fluorescence (LE-XRF) are used to characterize Ge content, while in-line High Resolution X-Ray Diffraction (HRXRD) is used to characterize strain. Because both patterned and un-patterned structures were investigated, scatterometry (also called optical critical dimension, or OCD) is used to provide valuable geometrical metrology.

The focused ion beam (FIB) has become an important tool for micro- and nanostructuring of samples such as milling, deposition and imaging. However, this leads to damage of the surface on the nanometer scale from implanted projectile ions and recoiled material atoms. It is therefore important to investigate each kind of damage quantitatively. We present a dynamic Monte-Carlo (MC) simulation code to simulate the morphological and compositional changes of a multilayered sample under ion irradiation and a molecular dynamics (MD) simulation code to simulate dose-dependent changes in the backscattering-ion (BSI)/secondary-electron (SE) yields of a crystalline sample. Recent progress in the codes for research to simulate the surface morphology and Mo/Si layers intermixing in an EUV lithography mask irradiated with FIBs, and the crystalline orientation effect on BSI and SE yields relating to the channeling contrast in scanning ion microscopes, is also presented.

New critical dimension metrology methods such as critical dimension small angle X-ray scattering (CDSAXS) are being developed to meet the measurement challenges of next generation devices. Two key requirements for any new CD metrology method are non-destructiveness and the measurement speed. We will report on a study of beam damage and scattering strength of two model photoresist systems, HSQ and PMMA. We also will report on the status and initial results from NIST’s upgraded lab CDSAXS system. 50 nm pitch line gratings were fabricated in HSQ and PMMA films using EUV interference lithography at the Swiss Light Source. The lines were about 30 nm tall and 20-30 nm wide. The 17 keV CDSAXS exposure time was varied from 0.1 s to 60 s to determine the minimum X-ray exposure required to obtain a satisfactory fit. Normal incident measurements separated by a blanket X-ray exposure were repeated to measure the decrease in scattering intensity with X-ray dose. The PMMA scattering signal was found to decrease by about 80 % before stabilizing at around 15 % of the original scattering intensity. The HSQ scattering signal decreased much less and stabilized at about 80 % of the original scattering intensity. We also conducted a series of variable-angle CDSAXS measurements as a function of blanket X-ray exposure to determine how the shape of the photoresist lines changed during X-ray exposure. For PMMA, we found the line width to remain constant and the line height to decrease from 25 nm to 10 nm during the exposure series. The exposures that damaged the samples corresponded to several hours of exposure to the synchrotron beam in a 100 µm spot and were much longer than what was required to characterize the line gratings. Smaller targets result in a larger dose and could potentially damage the resist in the time required to make a CDSAXS measurement. The large differences in beam damage between PMMA and HSQ show that resist damage from CDSAXS will depend on the particular resist chemistries and target size.

Nanoimprint lithography (NIL) is one alternative lithography solution that is being pursued by the industry. A metrology-related problem specific to NIL is the measurement of the residual layer thickness (RLT), as knowledge of this is key to the monitoring and control of the NIL process and subsequent patterning. Scatterometry is used to measure the RLT due to its ability to measure profile features non-destructively with high throughput. But because scatterometry is sensitive to features unrelated to the parameter of interest, complex geometries throughout the film stack can make the measurement challenging. New methods to reduce the impact of such complex geometries on the measurement parameters of interest are therefore needed. Because of the use of NIL for 3DNAND development, the measurement of the RLT with complex structures underneath becomes necessary. This paper describes the results from a new hybrid metrology method that can combine key information from these complex geometries with scatterometry measurements to reduce the impact on the RLT measurement due to the layers beneath the resist. By reducing this impact, scatterometry measurement noise and cross-correlation of parameters are reduced, resulting in better precision and accuracy in the RLT measurement.

Analysis of hotspots is becoming more and more critical as we scale from node to node. To define true process windows at sub-14 nm technology nodes, often defect inspections are being included to weed out design weak spots (often referred to as hotspots). Defect inspection sub 28 nm nodes is a two pass process. Defect locations identified by optical inspection tools need to be reviewed by review-SEM’s to understand exactly which feature is failing in the region flagged by the optical tool. The images grabbed by the review-SEM tool are used for classification but rarely for quantification. The goal of this paper is to see if the thousands of review-SEM images which are existing can be used for quantification and further analysis. More specifically we address the SEM quantification problem with connected component analysis.

The semiconductor industry has continually sought the approaches to produce memory devices with increased memory cells per memory die. One way to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories is 3D stacked flash cell array. In constructing 3D NAND flash memories, increasing the number of stacked layers to build more memory cell number per unit area necessitates many high-aspect-ratio etching processes accordingly the incorporation of thick and unique etching hard-mask scheme has been indispensable. However, the ever increasingly thick requirement on etching hard-mask has made the hard-mask film stress control extremely important for maintaining good process qualities. The residual film stress alters the wafer shape consequently several process impacts have been readily observed across wafer, such as wafer chucking error on scanner, film peeling, materials coating and baking defects, critical dimension (CD) non-uniformity and overlay degradation. This work investigates the overlay and residual order performance indicator (ROPI) degradation coupling with increasingly thick advanced patterning film (APF) etching hard-mask. Various APF films deposited by plasma enhanced chemical vapor deposition (PECVD) method under different deposition temperatures, chemicals combinations, radio frequency powers and chamber pressures were carried out. And -342MPa to +80MPa film stress with different film thicknesses were generated for the overlay performance study. The results revealed the overlay degradation doesn’t directly correlate with convex or concave wafer shapes but the magnitude of residual APF film stress, while increasing the APF thickness will worsen the overlay performance and ROPI strongly. High-stress APF film was also observed to enhance the scanner chucking difference and lead to more serious wafer to wafer overlay variation. To reduce the overlay degradation from ever increasingly thick APF etching hard-mask, optimizing the film stress of APF is the most effective way and high order overlay compensation is also helpful.

With the integration of high speed Scanning Electron Microscope (SEM) based Automated Defect Redetection (ADR) in both high volume semiconductor manufacturing and Research and Development (R and D), the need for reliable SEM Automated Defect Classification (ADC) has grown tremendously in the past few years. In many high volume manufacturing facilities and R and D operations, defect inspection is performed on EBeam (EB), Bright Field (BF) or Dark Field (DF) defect inspection equipment. A comma separated value (CSV) file is created by both the patterned and non-patterned defect inspection tools. The defect inspection result file contains a list of the inspection anomalies detected during the inspection tools’ examination of each structure, or the examination of an entire wafers surface for non-patterned applications. This file is imported into the Defect Review Scanning Electron Microscope (DRSEM). Following the defect inspection result file import, the DRSEM automatically moves the wafer to each defect coordinate and performs ADR. During ADR the DRSEM operates in a reference mode, capturing a SEM image at the exact position of the anomalies coordinates and capturing a SEM image of a reference location in the center of the wafer. A Defect reference image is created based on the Reference image minus the Defect image. The exact coordinates of the defect is calculated based on the calculated defect position and the anomalies stage coordinate calculated when the high magnification SEM defect image is captured. The captured SEM image is processed through either DRSEM ADC binning, exporting to a Yield Analysis System (YAS), or a combination of both. Process Engineers, Yield Analysis Engineers or Failure Analysis Engineers will manually review the captured images to insure that either the YAS defect binning is accurately classifying the defects or that the DRSEM defect binning is accurately classifying the defects. This paper is an exploration of the feasibility of the utilization of a Hitachi RS4000 Defect Review SEM to perform Automatic Defect Classification with the objective of the total automated classification accuracy being greater than human based defect classification binning when the defects do not require multiple process step knowledge for accurate classification. The implementation of DRSEM ADC has the potential to improve the response time between defect detection and defect classification. Faster defect classification will allow for rapid response to yield anomalies that will ultimately reduce the wafer and/or the die yield.

In recent years, lithographic printability of overlay metrology targets for memory applications has emerged as a significant issue. Lithographic illumination conditions such as extreme dipole, required to achieve the tightest possible pitches in DRAM pose a significant process window challenge to the metrology target design. Furthermore, the design is also required to track scanner aberration induced pattern placement errors of the device structure. Previous workiii, has shown that the above requirements have driven a design optimization methodology which needs to be tailored for every lithographic and integration scheme, in particular self-aligned double and quadruple patterning methods. In this publication we will report on the results of a new target design technique and show some example target structures which, while achieving the requirements specified above, address a further critical design criterion – that of process resilience.

Overlay control for semiconductor devices is getting tighter in recent years. In the past, we may only concern the whether the overlay are in spec or not. However, the spec we concerned was the same for both X and Y directions. To achieve the tighter spec in the future, we may consider the asymmetry specs for X and Y directions separately for some specific layers, such as CONT layer. For example, if the spec of X direction is tighter than Y direction, we can lose the precision of overlay from Y direction to let overlay from X direction more precise. Theoretically, the common overlay models such as HOPC or iHOPC set X and Y directions independently. To reach the goal of loss overly from one direction to preserve the overlay from the other direction, we consider the full map measurement overlay historical data. From these data, we can analyze the data to find which overlay targets are more important to X direction, and we can set these corresponding targets as the new measurement locations. This is one concept of “asymmetry” since the chosen measurement locations can provide more precisely correction for the overlay of specific direction. On the other hand, we use the in spec ratio (ISR) index for all measurement overlay targets on wafer to replace the traditional mean plus 3 sigma (M3S) index, since we have the budgets of both X and Y directions. The in spec ratio is defined as ratio that the residuals of X and Y directions fill the corresponding budgets, simultaneously. Since our goal is to maximize the ISR, the traditional M3S optimization algorithm can be replaced by ISR optimization with different overlay specs. That is the reason we call “asymmetry overlay correction”.

The semiconductor industry current standard of focus setup and control can be improved by the implementation of diffraction-based focus (DBF) marks and their applications. Determining best focus per scanner/reticle/device/layer (SRDL) combination is currently done by exposing a focus/energy matrix (FEM) wafer and examining CD features. The drawback of this process of record (POR) method is that the accuracy is greatly influenced by inter- and intra-field effects, focus step size, and machine accuracy. However, DBF marks do not suffer from these drawbacks because they are measured on product and close to the CD features. Experiments confirm that when comparing Bossung curves on each scanner, the wafer-to-wafer variation is much lower using DBF. The setup time and accuracy of new SRDL combinations can also be greatly improved using DBF. DBF uses an asymmetry signal which is translated directly to focus values and is independent of any focus settings of the scanner. After accurately determining the best focus using DBF on only one SRDL combination, the focus setting can be applied to all other combinations and scanners will be matched. Instead of exposing a FEM for each SRDL combination, best focus only needs to be determined once. Experiments using five different machine/reticle combinations show that Bossung tops can be matched with significantly more accuracy compared to POR. Experiments also show a linear relation between energy and shift in Bossung top; both DBF and CD are sensitive to energy variation. When correcting for energy differences, the Bossung top scanner-to-scanner matching accuracy can be improved further. A method using DBF for scanner best focus matching saves up to 10 hours of CD-SEM and manpower setup time per SRDL combination. When a scanner needs to be requalified, the same DBF focus setup method can be used, reducing the scanner downtime.

This study explores the feasibility of utilizing the high throughput non-destructive inspection by Surface Scanning Inspection System (SSIS) of copper wafers to monitor the quality of the copper seeding and electroplating process. Currently copper grain size and surface quality is measured by atomic force microscope (AFM). While AFM provides high resolution information down to 1 um² it is highly time intensive inspection of a single wafer taking up to 20 minutes. The SSIS in this study provides fast full wafer surface roughness information in 450um × 450um blocks. This paper will also investigate the advantages of identifying wafer level process variation of the copper film deposition with the SSIS versus sampled points of AFM inspection. With full wafer surface roughness information it may be possible to find a commonality between the quality of the copper electroplating process based up on the haze information of the copper seeding wafer.

On-product overlay requirements are becoming more challenging with every next technology node due to the continued decrease of the device dimensions and process tolerances. Therefore, current and future technology nodes require demanding metrology capabilities such as target designs that are robust towards process variations and high overlay measurement density (e.g. for higher order process corrections) to enable advanced process control solutions. The impact of advanced control solutions based on YieldStar overlay data is being presented in this paper. Multi patterning techniques are applied for critical layers and leading to additional overlay measurement demands. The use of 1D process steps results in the need of overlay measurements relative to more than one layer. Dealing with the increased number of overlay measurements while keeping the high measurement density and metrology accuracy at the same time presents a challenge for high volume manufacturing (HVM). These challenges are addressed by the capability to measure multi-layer targets with the recently introduced YieldStar metrology tool, YS350. On-product overlay results of such multi-layers and standard targets are presented including measurement stability performance.

During the last few decades, the semiconductor industry has been able to scale device performance up while driving costs down. What started off as simple geometrical scaling, driven mostly by advances in lithography, has recently been accompanied by advances in processing techniques and in device architectures. The trend to combine efforts using process technology and lithography is expected to intensify, as further scaling becomes ever more difficult. One promising component of future nodes are “scaling boosters”, i.e. processing techniques that enable further scaling. An indispensable component in developing these ever more complex processing techniques is semiconductor process modeling software. Visualization of complex 3D structures in SEMulator3D, along with budget analysis on film thicknesses, CD and etch budgets, allow process integrators to compare flows before any physical wafers are run. Hundreds of “virtual” wafers allow comparison of different processing approaches, along with EUV or DUV patterning options for defined layers and different overlay schemes. This “virtual fabrication” technology produces massively parallel process variation studies that would be highly time-consuming or expensive in experiment. Here, we focus on one particular scaling booster, the fully self-aligned via (FSAV). We compare metal-via-metal (mevia-me) chains with self-aligned and fully-self-aligned via’s using a calibrated model for imec’s N7 BEoL flow. To model overall variability, 3D Monte Carlo modeling of as many variability sources as possible is critical. We use Coventor SEMulator3D to extract minimum me-me distances and contact areas and show how fully self-aligned vias allow a better me-via distance control and tighter via-me contact area variability compared with the standard self-aligned via (SAV) approach.

Continuous tightening of the overlay control budget in the semiconductor industry drives the need for improved overlay metrology capabilities. In this context, measurement accuracy needs to be addressed. The first part this study shows that Diffraction Based Overlay metrology accuracy can be improved with a dedicated methodology. This methodology involves the use of target design simulation software in order to maximize stack sensitivity and to minimize processes non uniformity impact on the measurement. In the second part this study focuses on Holistic Metrology Qualification (HMQ) methodology that allows selecting the best on-wafer target. The methodology is explained and discussed. It is demonstrated that HMQ helps to reduce target asymmetry impact on measurement uncertainty and to select primary recipe parameters (wavelength, polarization, etc…). Finally CD-SEM measurements were used to validate methodology results.

ASML AH53 and AH74 with higher odd-order diffraction light are the widely used alignment marks in industry to achieve better alignment accuracy by reducing mark damage noise. During lithography alignment process, decent diffraction light power is the basic demand. However, with the use of some high absorption (k is not equal to 0 for detective wavelength) material, it is difficult to detect the light power reflecting from the thick and opaque film stacks with these standard alignment marks. Here we optimized four alignment marks with higher odd-order diffraction power with comparing with AH53 and AH74. One software based on Fourier optical theory is built to quickly calculate the wafer quality (WQ) of different film stacks and different alignment marks. ASML SMASH alignment system can accept customized alignment mark, with new mark type configuration file. In order to demonstrate the effectiveness of new alignment marks, we put the marks on a mask and do the experiments to compare with simulation results. All the experiments results show that new designed alignment marks have larger WQs of odd-order diffraction.

Optical metrology tool, LX530, is designed for high throughput and dense sampling metrology in semiconductor manufacture. It can inspect the dose and focus variation in the process control based on the critical dimension (CD) and line edge roughness (LER) measurement. The working principle is shown with a finite-difference-time-domain (FDTD) CD simulation. Two optical post lithography wafers, including one focus-exposure-matrix (FEM) wafer and one nominal wafer, are inspected for CD, dose and focus analysis. It is demonstrated that dose and focus can be measured independently. A data output method based on global CD uniformity (CDU), inter CDU and intra CDU is proposed to avoid the data volume issue in dense sampling whole wafer inspection.

In the advent of multiple patterning techniques in semiconductor industry, metrology has progressively become a burden. With multiple patterning techniques such as Litho-Etch-Litho-Etch and Sidewall Assisted Double Patterning, the number of processing step have increased significantly and therefore, so as the amount of metrology steps needed for both control and yield monitoring. The amount of metrology needed is increasing in each and every node as more layers needed multiple patterning steps, and more patterning steps per layer. In addition to this, there is that need for guided defect inspection, which in itself requires substantially denser focus, overlay, and CD metrology as before. Metrology efficiency will therefore be cruicial to the next semiconductor nodes. ASML's emulated wafer concept offers a highly efficient method for hybrid metrology for focus, CD, and overlay. In this concept metrology is combined with scanner's sensor data in order to predict the on-product performance. The principle underlying the method is to isolate and estimate individual root-causes which are then combined to compute the on-product performance. The goal is to use all the information available to avoid ever increasing amounts of metrology.

Overlay metrology setup today faces a continuously changing landscape of process steps. During Diffraction Based Overlay (DBO) metrology setup, many different metrology target designs are evaluated in order to cover the full process window. The standard method for overlay metrology setup consists of single-wafer optimization in which the performance of all available metrology targets is evaluated. Without the availability of external reference data or multiwafer measurements it is hard to predict the metrology accuracy and robustness against process variations which naturally occur from wafer-to-wafer and lot-to-lot. In this paper, the capabilities of the Holistic Metrology Qualification (HMQ) setup flow are outlined, in particular with respect to overlay metrology accuracy and process robustness. The significance of robustness and its impact on overlay measurements is discussed using multiple examples. Measurement differences caused by slight stack variations across the target area, called grating imbalance, are shown to cause significant errors in the overlay calculation in case the recipe and target have not been selected properly. To this point, an overlay sensitivity check on perturbations of the measurement stack is presented for improvement of the overlay metrology setup flow. An extensive analysis on Key Performance Indicators (KPIs) from HMQ recipe optimization is performed on µDBO measurements of product wafers. The key parameters describing the sensitivity to perturbations of the measurement stack are based on an intra-target analysis. Using advanced image analysis, which is only possible for image plane detection of μDBO instead of pupil plane detection of DBO, the process robustness performance of a recipe can be determined. Intra-target analysis can be applied for a wide range of applications, independent of layers and devices.

To produce high-end semiconductor products, clean vacuum is often required. Even small amounts of high-mass molecules can reduce product yield. The challenge is to timely detect the presence of relevant contaminants. This is where MFIG can help. The mass-filtered ion gauge sensor (MFIG) continuously and selectively monitors the presence of high-mass contaminant molecules with a sensitivity down to 1E-13 mbar at total pressures up to 1E-5 mbar. This contribution presents laboratory and field-test data to demonstrate the capabilities of the latest version of the MFIG sensor in continuously and selectively detecting high-mass contaminant molecules in (U)HV vacuum.

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked flash cell array has been proposed. In constructing 3D NAND flash memories, the higher bit number per area is achieved by increasing the number of stacked layers. Thus the so-called “staircase” patterning to form electrical connection between memory cells and word lines has become one of the primarily critical processes in 3D memory manufacture. To provide controllable critical dimension (CD) with good uniformity involving thick photo-resist has also been of particular concern for staircase patterning. The CD uniformity control has been widely investigated with relatively thinner resist associated with resolution limit dimension but thick resist coupling with wider dimension. This study explores CD uniformity control associated with thick photo-resist processing. Several critical parameters including exposure focus, exposure dose, baking condition, pattern size and development recipe, were found to strongly correlate with the thick photo-resist profile accordingly affecting the CD uniformity control. To minimize the within-wafer CD variation, the slightly tapered resist profile is proposed through well tailoring the exposure focus and dose together with optimal development recipe. Great improvements on DCD (ADI CD) and ECD (AEI CD) uniformity as well as line edge roughness were achieved through the optimization of photo resist profile.

As the demand of the technology node shrinks from 14nm to 7nm, the reliability of tool monitoring techniques in advanced semiconductor fabs to achieve high yield and quality becomes more critical. Tool health monitoring methods involve periodic sampling of moderately processed test wafers to detect for particles, defects, and tool stability in order to ensure proper tool health. For lithography TWINSCAN scanner tools, the requirements for overlay stability and focus control are very strict. Current scanner tool health monitoring methods include running BaseLiner to ensure proper tool stability on a periodic basis. The focus measurement on YIELDSTAR by real-time or library-based reconstruction of critical dimensions (CD) and side wall angle (SWA) has been demonstrated as an accurate metrology input to the control loop. The high accuracy and repeatability of the YIELDSTAR focus measurement provides a common reference of scanner setup and user process. In order to further improve the metrology and matching performance, Diffraction Based Focus (DBF) metrology enabling accurate, fast, and non-destructive focus acquisition, has been successfully utilized for focus monitoring/control of TWINSCAN NXT immersion scanners. The optimal DBF target was determined to have minimized dose crosstalk, dynamic precision, set-get residual, and lens aberration sensitivity. By exploiting this new measurement target design, ~80% improvement in tool-to-tool matching, >16% improvement in run-to-run mean focus stability, and >32% improvement in focus uniformity have been demonstrated compared to the previous BaseLiner methodology. Matching <2.4 nm across multiple NXT immersion scanners has been achieved with the new methodology of set baseline reference. This baseline technique, with either conventional BaseLiner low numerical aperture (NA=1.20) mode or advanced illumination high NA mode (NA=1.35), has also been evaluated to have consistent performance. This enhanced methodology of focus control and monitoring on multiple illumination conditions, opens an avenue to significantly reduce Focus-Exposure Matrix (FEM) wafer exposure for new product/layer best focus (BF) setup.

With the latest immersion scanners performing at the sub-2 nm overlay level, the non-lithography contributors to the OnProduct-Overlay budget become more and more dominant. Examples of these contributors are etching, thin film deposition, Chemical-Mechanical Planarization and thermal anneal. These processes can introduce stress or stress changes in the thin films on top of the silicon wafers, resulting in significant wafer grid distortions. High-order wafer alignment (HOWA) is the current ASML solution for correcting wafers with a high order grid distortion introduced by non-lithographic processes, especially when these distortions vary from wafer-to-wafer. These models are currently successfully applied in high volume production at several semiconductor device manufacturers. An important precondition is that the wafer distortions remain global as the polynomial-based HOWA models become less effective for very local distortions. Wafer-shape based feed forward overlay corrections can be a possible solution to overcome this challenge. Thin film stress typically has an impact on the unclamped, free-form shape of the wafers. When an accurate relationship between the wafer shape and in-plane distortion (IPD) after clamping is established then feedforward overlay control can be enabled. In this work we assess the capability of wafer-shape based IPD predictions via a controlled experiment. The processinduced IPDs are accurately measured on the ASML TWINSCANTM system using its SMASH alignment system and the wafer shapes are measured on the Superfast 4G inspection system. In order to relate the wafer shape to the IPD we have developed a prediction model beyond the standard Stoney approximation. The match between the predicted and measured IPD is excellent (~1-nm), indicating the feasibility of using wafer shape for feed-forward overlay control.

Multi-patterning processes have become common in the leading-edge semiconductor industry. These processes require a good patterning uniformity over the wafer while different process steps have impact. The initial lithography steps can be nearly perfect, but the CD variation after a trim process may cause CD variation after the spacer deposition. In fact, that leads to final non-uniformity of the final CD. Monitoring and controlling the individual CD parameters is not sufficient to ensure a stable process. We define a set of new KPIs, taking all contributions into account and using macro measurement data. We show that a reliable monitoring is achieved to meet the process specifications.

This paper has developed the multi-beam laser interference lithography (LIL) system for nano/micro pattern sapphire substrate process (PSS/NPSS). However, the multi-beam LIL system is very sensitive to the light source and the vibration. When there is a vibration source in the exposure environment, the standing wave distribution on the substrate will be affected by the vibration and move in a certain angle. As a result, Moiré fringe defects occur on the exposure result. In order to eliminate the effect of the vibration, we use the software ANSYS to analyze the resonant frequencies of our multi-beam LIL system. Therefore, we need to design new multi-beam LIL system to raise the value of resonant frequencies. The new design of the multi-beam LIL system has higher resonant frequencies and successfully eliminates the bending and rotating effect of the resonant frequencies. As a result, the new multi-beam LIL system can fabricate large area and defects free period structures.

Mask inspection is a critical step in the mask manufacturing process in order to ensure all dimensions printed are within the needed tolerances. This becomes even more challenging as the device nodes shrink and the complexity of the tapeout increases. Thus, the amount of measurement points and their critical dimension (CD) types are increasing to ensure the quality of the mask. In addition to the mask quality, there is a significant amount of manpower needed when the preparation and debugging of this process are not automated. By utilizing a novel pattern search technology with the ability to measure and report match region scan-line (edge) measurements, we can create a flow to find, measure and mark all metrology locations of interest and provide this automated report to the mask shop for inspection. A digital library is created based on the technology product and node which contains the test patterns to be measured. This paper will discuss how these digital libraries will be generated and then utilized. As a time-critical part of the manufacturing process, this can also reduce the data preparation cycle time, minimize the amount of manual/human error in naming and measuring the various locations, reduce the risk of wrong/missing CD locations, and reduce the amount of manpower needed overall. We will also review an example pattern and how the reporting structure to the mask shop can be processed. This entire process can now be fully automated.

Self-aligned quadruple patterning (SAQP) processes have found widespread acceptance in advanced technology nodes to drive device scaling beyond the resolution limitations of immersion scanners. Of the four spaces generated in this process from one lithography pattern two tend to be equivalent as they are derived from the first spacer deposition. The three independent spaces are commonly labelled as α, β and γ. α, β and γ are controlled by multiple process steps including the initial lithographic patterning process, the two mandrel and spacer etches as well as the two spacer depositions. Scatterometry has been the preferred metrology approach, however is restricted to repetitive arrays. In these arrays independent measurements, in particular of alpha and gamma, are not possible due to degeneracy of the standard array targets. . In this work we present a single target approach which lifts the degeneracies commonly encountered while using product relevant layout geometries. We will first describe the metrology approach which includes the previously described SRM (signal response metrology) combined with reference data derived from CD SEM data. The performance of the methodology is shown in figures 1-3. In these figures the optically determined values for alpha, beta and gamma are compared to the CD SEM reference data. The variations are achieved using controlled process experiments varying Mandrel CD and Spacer deposition thicknesses.

The application of Moiré effect for testing of a lithographic projection lens is reported. The arrangement presented allows measuring magnification, distortion, field curvature and telecentricity of the lens and can be used for its fine tuning. The method is based on two matched two-dimensional gratings, positioned in mutually conjugated planes; one of them can be translated. Visual interpretation of Moiré fringe pattern allows quick diagnostics of position errors exceeding critical dimension, whereas lateral scanning is applied for measuring of smaller magnitude errors. Field curvature and telecentricity are measured by 3D scanning. Presented results are in a good agreement with those obtained elsewhere.

As semiconductor manufacturing continues its march towards more advanced technology nodes, it becomes increasingly important to identify and characterize design weak points, which is typically done using a combination of inline inspection data and the physical layout (or design). However, the employed methodologies have been somewhat imprecise, relying greatly on statistical techniques to signal excursions. For example, defect location error that is inherent to inspection tools prevents them from reporting the true locations of defects. Therefore, common operations such as background-based binning that are designed to identify frequently failing patterns cannot reliably identify specific weak patterns. They can only identify an approximate set of possible weak patterns, but within these sets there are many perfectly good patterns. Additionally, characterizing the failure rate of a known weak pattern based on inline inspection data also has a lot of fuzziness due to coordinate uncertainty. SEM (Scanning Electron Microscope) Review attempts to come to the rescue by capturing high resolution images of the regions surrounding the reported defect locations, but SEM images are reviewed by human operators and the weak patterns revealed in those images must be manually identified and classified. Compounding the problem is the fact that a single Review SEM image may contain multiple defective patterns and several of those patterns might not appear defective to the human eye.

In this paper we describe a significantly improved methodology that brings advanced computer image processing and design-overlay techniques to better address the challenges posed by today’s leading technology nodes. Specifically, new software techniques allow the computer to analyze Review SEM images in detail, to overlay those images with reference design to detect every defect that might be present in all regions of interest within the overlaid reference design (including several classes of defects that human operators will typically miss), to obtain the exact defect location on design, to compare all defective patterns thus detected against a library of known patterns, and to classify all defective patterns as either new or known. By applying the computer to these tasks, we automate the entire process from defective pattern identification to pattern classification with high precision, and we perform this operation en masse during R & D, ramp, and volume production.

By adopting the methodology, whenever a specific weak pattern is identified, we are able to run a series of characterization operations to ultimately arrive at the root cause. These characterization operations can include (a) searching all pre-existing Review SEM images for the presence of the specific weak pattern to determine whether there is any spatial (within die or within wafer) or temporal (within any particular date range, before or after a mask revision, etc.) correlation and (b) understanding the failure rate of the specific weak pattern to prioritize the urgency of the problem, (c) comparing the weak pattern against an OPC (Optical Procimity Correction) Verification report or a PWQ (Process Window Qualification)/FEM (Focus Exposure Matrix) result to assess the likelihood of it being a litho-sensitive pattern, etc. After resolving the specific weak pattern, we will categorize it as known pattern, and the engineer will move forward with discovering new weak patterns.