A system used to provide linewidth control in a IC manufacturing facility is described. It combines the use of interferometry, real time endpoint detection, and automation to tighten linewidth distributions by adjusting development times. The use of Fourier Transforms provide consistent endpoint detection for a variety of part, process, and substrate types. The system increases throughput and reduces rework by eliminating the need for trial wafers. It also provides a means for process monitoring as well as a tool for troubleshooting, and process development. The paper describes the Automatic Linewidth Control System: its operation, algorithms for endpoint detection and its performance.

For many years the ability to measure dielectric films and then produce a graphic output either in contour map or 3-dimensional form has been either slow or time consuming in labor. With the new generation of equipment on the market this is no longer the case. This paper will describe the operation of this equipment in obtaining contour maps of several typical processes and the use of these maps in the evaluation of these processes and related equipment. The advantage of advanced computer technology also allows the data to be collated for the generation of process control charts within seconds of the collection of the data. The use of these control charts will also be demonstrated.

In the fully automated semiconductor integrated circuit fabrication facility of the future, individual fabrication processes are expected to be controlled, on-line, by intelligent systems. These systems will adjust process parameters based on a given process specification. The current state of a process will be supplied to these systems in part by intelligent sensors/inspection systems which will observe the product after it has been processed. These systems should be fast, nondestructive, automatic, and be able to work at high resolutions. For monitoring the etching and microlithography processes, a system that can extract integrated circuit pattern (sidewall) topography will be very useful. This paper presents our work on using automatic stereo, with scanning electron microscope (SEM) secondary electron images as input, for extracting integrated circuit pattern topography. In this paper following an introduction to the concept of shape from computer stereo vision, an algorithm that has been developed for this task will be discussed. The parallel implementation of this algorithm on an NCUBE multiprocessor will be discussed next. This will be followed by a presentation of results.

One of the critical processes in the fabrication of state-of-the-art VLSI MOS circuits is the polysilicon gate photolithography. The combination of near-micron or submicron design rules, substrate topography and substrate reflectivity imposes stringent requirements on the performance and latitude of the photopatterning process. Numerous techniques have been developed to enhance the performance of photolithographic processes, including the use of Multi-Layer Resist systems,^1-4 Anti-Reflective Coatings,19996 Contrast Enhancement Layers,^1,7 dyed resists,199 and Post-Exposure Bakes (PEB).9-11 Of primary concern is the control of resist feature critical dimensions (CDs). Control of CDs to within ± 10% of the nominal value is typically desired. Although many parameters have an effect on resist CDs, the major factor is usually the exposure dose. This study was undertaken in an effort to characterize the resist CD latitude as a function of exposure dose for four key Single Layer Resist processes: (1) Kodak 820 resist; (2) Kodak 820 resist with PEB; (3) dyed Kodak 820 resist; and (4) dyed Kodak 820 resist with PEB.

Absolute distortion measurement in stepping metrology is critical in optimizing wafer stepper performance. The conventional reduction wafer stepper method of determining absolute distortion relies on a single reticle field of adjustable size and on a high precision stage. Data to determine distortion is collected from "box in a box" registration structures by optical or electrical measurements. This method is inappropriate, or compromising, in determining distortion of a commercial 1X wafer stepper. The 1X wafer stepper has multiple reticle fields of fixed size and achieves accurate pattern overlay thru site by site alignment without a high precision stage. The vendor of the 1X stepper has developed a method of determining absolute distortion by imaging two reticles of identical distortion on the stepper and then superimposing the image of one reticle onto the other with a known offset. The site metrology system of the stepper is used to collect data to determine distortion. This paper evaluates a new method of determining distortion of a 1X wafer stepper. The new method combines the vendor concept of superimposed reticle images with data collection and analysis techniques of electrical "box in a box" registration structures thus eliminating any stage contributions to distortion. Results presented are compared with the distortion results obtained by the vendor.

The National Bureau of Standards (NBS) has had a continuing program to develop optical linewidth standards for the integrated circuit industry for over 10 years. The past work has concentrated on the development and the certification of photomask linewidth and pitch standards. The recent work is directed at extending the feature sizes on these standards to cover the range from 0.5 to 30 μm, and at doubling the certification accuracy to 0.025 μm. Features with heights larger than approximately 1/4 wavelength of light cannot be modeled as zero-thickness layers as is done for photomasks. The development of models to handle this thick-layer case and to develop practical edge-detection criteria are currently under development at NBS. However, at the present time, it is generally not possible to interpret the image profiles of thick features and thereby measure an accurate linewidth. The basic obstacles that must be overcome to achieve accurate submicrometer feature size measurements for these features will be reviewed and the prospects for future NBS optical standards for features such as photoresist lines on silicon wafers will be assessed. Some suggestions about what to do until these standards become available will be given.

A bright field optical microscope is modelled to identify the errors introduced into dimensional measurements by misalignments and aberrations. The effect of illumination misalignment is considered and it is demonstrated that unless the illumination cone is accurately centred on the optical axis there will be significant errors introduced into registration measurements. A comprehensive study is made of objective lens aberrations. Theoretical models are used to quantify the effects different aberration types have on image profiles and dimensional measurement errors. A practical study is also made of thirteen commercially available objectives and it is concluded that the amount of aberration present in many of these lenses is too large for many measurement applications. Theoretical tolerances for different aberration types are established. It is shown that by using an objective with only small levels of aberration and carefully aligning the microscope illuminator, it is possible to obtain image profiles of thin and thick (>200nm) layer objects which closely match those predicted by theory.

Although scanning electron microscopes (SEM) are usually used for measuring submicrometer critical dimensions (CD), the shortcomings of using an SEM for this purpose have prompted an investigation of the use of a new alternative, the confocal scanning laser microscope (CSLM). A SiScan-I instrument manufactured by SiScan Systems was used in this study. The most attractive features of a CSLM are its reliability, ease of use, and high precision. CDs as small as 0.5 pm can be measured on most samples with an instrumental precision of about 0.03μm (3 σ ). However, variable systematic errors may reduce the practical precision of the instrument if certain parameters are not tightly controlled from sample to sample. Results are presented that show how CD measurements are affected by the following key parameters: 1) thickness of the resist, 2) thickness of an underlying transparent layer, 3) size of the feature, and 4) slope of the edge wall of the resist. Although all of these parameters are found to affect the CSLM measurements, errors due to variations in parameters 1, 3, and 4 will probably be insignificant for a well controlled lithographig process.. Variations in parameter 2 are often less well controlled and systematic CD errors on the order of 100 to 200 A per 100 A of variation in the film thickness can be expected. Suggestions are made whereby operators can recognize and compensate for these types of systematic errors. It appears that CDs of most samples can be measured on a CSLM with an effective precision of about 0.05 μm (3σ ), which is comparable to that of an SEM based measuring system. This precision estimate includes 0.03 μm for random instrumental errors and up to 0.04 μm for systematic errors due to random variations in the sample.

Linewidth measurement using the scanning electron microscope is not well understood. The basic intent is to measure the size of a structure from the secondary and backscattered electron signal generated by that structure^1-6. Thus, an accurate measurement requires an understanding of how the profile and critical dimension of the line being measured relate to the electron signal. The complicating factor is that different features generate different signals and that surroundings often influence the detected signal from a given feature.

In this paper, we consider the application of low voltage scanning electron microscopy (SEM) to practical pilot line problems of critical dimension (CD) measurements and in-process wafer inspection of small geometry ( <2 pm) VLSI circuits . Two low voltage field emission CD measurement SEMs with automated wafer stages and computerized digital control CD systems were used. CD data from the SEM was compared with results from optical microscopy and electron probe metrology systems. Cross-calibration of CD data between the two SEMs was also analyzed using a variety of patterned layers. These included CD patterns measured after resist development and after etching of diffusion, poly Si gate, contact and metal layers in a 1.2 μm CMOS process. Examples of inprocess wafer inspection are presented. In addition, new applications of SEM metrology for sidewall spacer width and stepped contact CD measurements are demonstrated.

SEM measurement of uncoated samples is not as easy as the salesmen would like us to believe! Despite the relatively "simple" sample, optimizing for reproducible submicron linewidth measurements of polysilicon gates was not trivial. Beam energy was shown to control both the signal-to-noise and the slope of the measurement signal, while beam exposure time was found to cause systematic linewidth changes. Optimized measurements utilized a 2.3 kV beam energy, controlled beam exposure times, and a 60% threshold level. No damage was measured on MOS devices exposed at 2.3 kV, at least when such measurements were followed by the anneals typical for MOS process flows.

An electron beam metrology system has been used to study optical proximity effects in contrast-enhanced lithography. In this case, precision and differential measurement capability were found to be more important than absolute accuracy. Our results show distinct proximity effects due to retarded bleaching of the contrast enhancement layer over the smaller features and some additional anomalous effects which have been attributed to subtle changes in edge morphology. SEM micrographs of line-and-space patterns revealed sloped profiles at the smallest geometries near the Rayleigh limit of the exposure tool. Intermediate geometries had vertical profiles, and larger ones were re-entrant. Successful use of contrast enhancement for 0.7um CMOS devices required optimization of the process around a single critical dimension below one micrometer.

Digital filtering techniques have been combined with a scanning electron microscope to provide noise free, TV rate stereo images over the full magnification range of the SEM, giving a qualitative pseudo 3-D representation of the sample surface. In this paper, a development of this technique will be described which permits quantitative measurement of a surface in 3 dimensions. Image correlation techniques have been derived which, when coupled with the lens controls of the SEM in the form of a feedback loop, permit automatic profiling of small structures. The technique has potential applications to a range of integrated circuit inspection techniques including resist profiling and critical dimension measurements.

The continuous advance of microlithographic fabrication techniques into the submicron structure range requires a new generation of metrology systems to measure with an accuracy and throughput necessary for the demands of VLSI technology.

Realtime digital image processing of highly magnified optical images - Digital Microscopy - provides the basis for dramatic improvements in the rapid and repeatable acquisition of key process control information - CD's, registration, defect data. Metrology: Wafer and mask features down to .25u can now be repeatably measured optically. Techniques used in extending the minimum optical width measurement from ~l-1.5ji to .25|i will be discussed. Registration: Mask to wafer registration and layer to layer registration can now be measured with a standard deviation of .0033ji using box within a box or similar patterns. Inspection: High speed comparison to "golden" images stored in memory gives a quick look capability in addition to more extensive defect detection and coordinate determination capability. A variety of image processing functions will be discussed.

This paper describes a novel camera system to make precise measurements over a wide dynamic range of light intensities. The camera has been developed to provide measurements of very small (<1 micrometre) features on semiconductor wafers, observed through high-precision optical microscopes. As such, the system provides the basis of a high precision image acquisition system for use in an advanced line-width measuring instrument.

The precision and accuracy of the measurement tool or process used to determine a critical dimension (CD) are clearly important when considering the operational significance of the result. The presumption in CD measurements is that a single result is sought to represent the particular CD of the structure being imaged. Since this dimension may vary over the image this result is appropriately the average of the dimension, which is estimated based on a series of measurements. We discuss the use of the "confidence interval" as a measure of the "goodness" of a CD measurement and use the AMRAY SEM 1500 to illustrate and test our methods on 1-1.5μm lines. The measurement performance of this scanning electron microscope is shown to be extremely good (3 "sigma" better than 0.01μm), and the 95% confidence interval is shown to be a reliable measure of the practical accuracy of the CD measurement.

In the semiconductor field critical dimension (CD) measurement accuracies and repeat-abilities of 1% @ 3siqma are often required and supplied by instrument vendors. In a SEM the accuracy and repeatability of such measurements is related to the signal-to-noise (s/n) ratio of the signal carrying the topographical information of the feature. Noise sources associated with the irradiating beam, signal generation at the sample, signal collection and various signal processing techniques may have an effect on cd measurement statistics. Positional uncertainties of either the irradiating beam or the sample itself, will likewise contribute to c-d measurement uncertainties. This paper discusses the effects and require-ments of some of these noise sources - especially in the signal-intensity chain.

The diminishing size of VLSI features necessitates the use of a scanning electron microscope (SEM) for making inprocess CD measurements. The intent of this paper is to establish a methodology for improving the accuracy and precision of such measurements. In SEM metrology, the challenge lies in determining two points in the secondary electron line-scan corresponding to the feature edges. The systematic errors introduced by incorrect edge detection can be reduced greatly by optimizing the linescan with proper choice of SEM operating conditions. Experiments on two samples of interest in VLSI processing demonstrate the advantage of increased accelerating voltage for minimizing measuremental uncertainty. In addition, measuremental robustness, or sensitivity of linewidth measurement to SEM defocus, is shown to be strongly dependent upon the specific edge detection algorithm used.

The National Bureau of Standards has initiated a program to develop scanning electron microscope linewidth measurement standards for the integrated circuit community. This program involves the development of: a scanning electron microscope-based linewidth measurement and standard reference material certification instrument, the necessary electron beam/sample interaction modelling, and the appropriate micrometer and submicrometer artifacts. The basic problems that must be overcome to achieve accurate submicrometer feature size measurements in the scanning electron microscope for these artifacts will be reviewed and some suggestions of what can be done to "bridge-the-gap" until such standards become available will be given.

In the fully automated semiconductor integrated circuit (IC) fabrication facility of the future, individual fabrication processes are expected to be controlled on-line, by intelligent systems. The current state of a process will be supplied to these systems in part by intelligent sensors/inspection systems which will observe the product after it has been processed. These systems should be fast, nondestructive, automatic, and be able to work at high spatial resolutions. This paper describes a SEM based IC pattern shape inspection system which uses the design file of the IC as the reference model. The system is intended to identify discrepancies between the shapes of patterns transferred onto the wafer and the desired pattern shapes as stored in the design file. The algorithm uses a discrete optimization approach for finding the correspondence between image and model pattern boundary points. The paper will describe the proposed approach, present some result, and will also discuss parallel implementation issues.

It has been well established by previous work that high resolution electron-beam imaging is required to accurately measure dimensions near a micron and below. A brief overview of the applications for micrometrology system indicates that speed of operation or thruput is very important. A recently developed system is described which has been specifically designed for low voltage, high-speed micrometrology.

A practical approach for submicron lithography is mix and match imaging using x-ray and optical steppers. The advantages of x-ray lithography are primarily submicron resolution, unlimited depth of focus and insensitivity to substrate topology and composition. Optical lithography on the other hand becomes most difficult in the submicron region where process latitude becomes tightly limited. It seems reasonable to combine the cost advantage of optical lithography with the technical advantages of x-ray lithography by applying the x-ray technology to critical layers, difficult to image with optical steppers, for example, metal or polysilicon. In this approach, overlay between x-ray and optical levels is the pivotal issue, because it requires achieving an acceptable match between the grid irregularities of the two steppers used. The subject of this presentation is the characterization of a two level overlay in a mix and match lithography experiment involving a 10X optical stepper and a 1X x-ray stepper. Issues of field size differences, placement distortion in the optical and x-ray cases will be discussed. The overlay characterization and optimization method will be presented. Experimental results will be given and discussed.

Direct write E-beam lithography at 0.25 micron ground rules will soon be a practical reality. Other technologies such as X-Ray lithography are also moving rapidly towards these dimensions. This im-plies overlay tolerances at the level of 1 sigma = 25 nm. Characterization of tool overlay performance (particularly systematic error components) in this regime is a challenging and important metrology problem. A combination of carefully designed test structures, high quality fabrication, and the best available measuring instrumentation will be a minimum requirement for adequately addressing this need. This paper describes a study of self-compensating differential linewidth structures for such overlay measurements. These structures require only relative (not absolute) dimensional measurements, and linewidth comparisons are made only over very short physical distances. Therefore, the results are in principle insensitive to systematic errors and time-dependent drift in the metrology tool, and to systematic variations in processing uniformity across a macroscopic substrate. Design and fabrication of the test structures is discussed. The test structures used were primarily designed for use with an electrical linewidth measurement tool, but several more "traditional" overlay test structures were also built in for comparison purposes. The structures were exposed on an IBM EL-3 direct write E-beam tool with 0.25 - 0.5 micron ground rule capability, and delineated by RIE of 200 nm of doped polysilicon. The processing was optimized to produce lines with sharply defined vertical edges. Such lines give excellent signals in optical and SEM linewidth measurement tools, and so are well suited for comparison of these techniques with electrical measurements. Comparisons of linewidth differences measured electrically, laser optically, and on an SEM show excellent agreement. The 1 sigma measurement error is found to be in the range 7 - 9 nm for all of the three tools investigated. This remarkable performance clearly demonstrates the advantages of self-compensating structures. It is concluded that, given high quality test structure fabrication, all of these techniques are adequate for the purpose. Therefore, considerations of cost, throughput, and the real estate demands of the test structures would govern a practical choice of measurement technique. These factors are discussed in general terms. The measured linewidth differences which include overlay errors are compared with a sample population of linewidth differences, from the same areas of the wafer, which include only processing and measurement errors. For a sample size of about 100, the variance of the overlay sample (sigma = 31 nm) is more than 5 times that of the reference sample (sigma = 13 nm). Thus, the overlay errors of interest account for more than 80% of the variance in the measured results. Overlay vector plots measured by the differential technique are compared with those measured from optical verniers and from "Nestled L's" (a non-self-compensating test structure).The agreement is poor. Reasons for the inadequacy of these alternative structures are discussed. The value of these high-resolution overlay measurements is illustrated by presentation of vector plots of systematic and random overlay errors for a high resolution IBM EL-3 tool.

In this paper, state-of-the-art integrated circuit micrometrology techniques are described for linewidth control measurements and process control/repeatability of the image reversal process of photoresist AZ1470 by direct-write electron beam lithography. The micrometrology measurements involve electrical (Prometrix) and electron-optical (SEM) methods applied to submicron CMOS prototype VLSI circuits. Results obtained by these metrology techniques are presented and compared. The electron beam direct writer is a Cambridge EBMF6.5 system vector scan electron beam machine capable of achieving ultrahigh current densities with a beam of circular cross section and a gaussian intensity profile operated at 20 kev. The etched pattern linewidth accuracy for this electron beam lithography system is determined by errors related to: (a) resist-process, (b) e-beam machine and (c) proximity effect. This paper mainly deals with the analysis of such resist-process related errors, though machine related and proximity effect related errors are also discussed. The resist-process related errors stem from five sources: 1) soft bake temperature effect, 2) e-beam exposure dose, 3) ultraviolet flood exposure dose, 4) development processing and 5) etching uniformity. We have made separate determination of each error through critical dimension control measurements. It was found that e-beam dose, and development processes contributed the most to the process related errors. Our results show that there is close agreement between the electrical and SEM measurements within the accuracy of each technique. This image reversal process consistently produces critical dimension uniformity of one sigma (la) values of about 0.05μm. The linewidths are controlled within 10%. Thus, the results from the metrology data indicate that this resist process can be used to fabricate 0.5μm polysilicon gate structures (although isolated polygate features as small as 0.25μm can be achieved).

The results of varying dry polysilicon etch process parameters are presented. Techniques used to study and interpret the results are electrical linewidth measurement and thin film thickness measurement. Conclusions are drawn about the suitability of the process for specific design rule considerations, and the tolerance of the parameters involved.

Statistical monitoring and control procedures are essential components of VLSI manufacturing operations. Inspection of defects, measurement of critical dimensions and measurement of registration overlay are the traditional methods of monitoring and controlling a photolithography process. This paper will focus on one function of a fully automated inspection system being developed by OSI; the automated detection of defects on multilayer patterned wafers with textured thin films. A system architecture is described consisting of integrated mechanical, electrical, optical and software components that have been tailored to the inspection of semiconductor device micropatterns. A brief review of vision algorithms is presented along with a comparison of the template matching approach and a new method introduced by OSI. The discussion includes the effects of normal process variations and texture of device patterns on defect detection and false defect rates. Finally, the paper will describe the methods in which the data is analyzed and presented to production personnel to establish a rapid means of monitoring and controlling the photolithography process.

An automated test wafer procedure has been developed using the KLA 2020 wafer inspector to measure registration and critical dimensions on production wafers. The procedure reduces operator interactions to loading the wafer and entering information for wafer identification. The analysis of the registration data is performed on a PC using the methods established by Perloff to determine both intrafield and grid errors. These results are then used to correct the stepper. CD data is also analyzed by the program and corrections to the exposure time are calculated. It was found that the KLA 2020 is as much as 10 times faster and 4 times more precise in obtaining registration data then an operator reading optical verniers on a microscope. Due to the high precision of the reading, the analysis does not need a large number of readings to obtain precise and accurate stepper corrections. Further, significant improvements can be obtained by adding registration targets to measure the intrafield errors. Using the KLA 2020 and computer analysis we have demonstrated an ability to reduce the errors for a manually aligned run to a one sigma distribution of 0.09 um for x and y translation, 0.4 PPM for scaling and orthogonality, and 2.3 PPM for rotation from the first test wafer for a GCA 6100. Nearly all of this variation is due to operator misalignment or the inability of the stepper to correct the errors. The corrections with this technique measuring the same wafer are precise to + 0.01 um in translation and + 0.5 PPM for rotation, scaling, and orthogonality. It has also been shown that a simple linear equation can be used to correct exposure time, even when a process is not tightly controlled.

The results of recent research on synthetic electro-optic imaging using a Linnik interference microscope are presented. A new technique is used in which images are produced by calculating the degree of coherence between corresponding pixels in the object and reference image planes of the Linnik microscope. Each pixel in the synthetic image is a function of this degree of coherence. This amounts to what one might call "Coherence Probe Imaging." The images have the properties that all parts of the object which are out of focus appear dark, those in focus appear bright, and the depth of focus is very narrow. Three dimensional images can be produced by moving the object in the vertical direction and recording a number of optical sections of the image. Theoretical analyses and experimental results are presented. A model for the per-formance of the coherence probe microscope is first developed and then its performance is compared with that of a standard microscope and of a confocal laser scanning microscope within the context of this model. One figure shows the measured edge profile of a coherence probe microscope compared with a standard microscope for a clean edge of cleaved single crystal silicon. Another figure shows the measured z profile of the coherence probe microscope. Linewidth measurement algorithms are implemented on 3 dimensional images produced by the coherence probe microscope, and these measure the top width, the bottom width, and the height of the semiconductor lines independently. The amount of electronic hardware required for reasonable throughput is not prohibitive. Some results of comparison with Scanning Electron Microscopes are presented. Generally, the agreement is very good. Overall, the coherence probe microscope appears to have some promise for linewidth measurement applications. Several photographs show small defects on semiconductor devices as imaged by a coherence probe microscope and by a standard microscope, both illuminated with white light. Substantial resolution improvement is clearly discernable in these pictures suggesting that the coherence probe microscope may also be a promising imaging tool for defect detection.

Off-line quality control is a systematic method of optimizing production processes and product designs. It is widely used in Japan to produce high quality products at low cost. The method was introduced to us by Professor Genichi Taguchi who is a Deming-award winner and a former Director of the Japanese Academy of Quality. In this paper we will i) describe the off-line quality control method, and ii) document our efforts to optimize the process for forming contact windows in 3.5 Aim CMOS circuits fabricated in the Murray Hill Integrated Circuit Design Capability Laboratory. In the fabrication of integrated circuits it is critically important to produce contact windows of size very near the target dimension. Windows which are too small or too large lead to loss of yield. The off-line quality control method has improved both the process quality and productivity. The variance of the window size has been reduced by a factor of four. Also, processing time for window photolithography has been substantially reduced. The key steps of off-line quality control are: i) Identify important manipulatable process factors and their potential working levels. ii) Perform fractional factorial experiments on the process using orthogonal array designs. iii) Analyze the resulting data to determine the optimum operating levels of the factors. Both the process mean and the process variance are considered in this analysis. iv) Conduct an additional experiment to verify that the new factor levels indeed give an improvement.

The development of robust photolithography processes requires methodologies for efficiently finding operating conditions that will minimize the sensitivity of critical dimension control to the effects of inevitable manufacturing variability. Photolithography modeling coupled with a Monte Carlo sampling scheme and contemporary statistical design techniques accelerate the identification of the best operating conditions by reducing the number of needed process development experiments.

Recently there have been numerous papers, articles and books on the benefits and rewards of Statistical Process Control for manufacturing processes. Models are used that quite adequately describe methods appropriate for the factory situation where many discrete and identical items are turned out and where a limited number of parameters are inspected along the line. Photolithographic applications often require different statistical models from the usual factory methods. The difficulties encountered in getting started with SPC lie in determining: 1. what parameters should be tracked 2. what statistical model is appropriate for each of those parameters 3. how to use the models chosen. This paper describes three statistical models that, among them, account for most operations within a photolithographic manufacturing application. The process of determining which model is appropriate is described, along with the basic rules that may be used in making the determination. In addition, the application of each method is shown, and action instructions are covered. Initially the "x-bar, R" model is described. This model is the one most often found in off-the-shelf software packages, and enjoys wide applications in equipment tracking, besides general use process control. Secondly the "x, moving-R" model is described. This is appropriate where a series of measurements of the same parameter is taken on a single item, perhaps at different locations, such as in dimensional uniformity control for wafers or photomasks. In this case, each "x" is a single observation, or a number of measurements of a single observation, as opposed to a mean value taken in a sampling scheme. Thirdly a model for a Poisson distribution is described, which tends to fit defect density data, particulate counts, where count data is accumulated per unit or per unit time. The purpose of the paper is to briefly describe the included models, for those with little or no background in statistics, to enable them to begin to implement statistical process control and to reap the benefits of a controlled process, prior to, or without investing large amounts of time in training beforehand.

In processing a semiconductor product (from discrete devices up to the most complex products produced) we find more photolithographic steps in wafer fabrication than any other kind of process step. Thus, the success of a semiconductor manufacturer hinges on the optimization of their photolithographic processes. Yet, we find few companies that have taken the time to properly characterize this critical operation; they are sitting in the "passenger's seat", waiting to see what will come out, hoping that the yields will improve someday. There is no "black magic" involved in setting up a process at its optimum conditions (i.e. minimum sensitivity to all variables at the same time). This paper gives an example of a real world situation for optimizing a photolithographic process by the use of a properly designed experiment, followed by adequate multidimensional analysis of the data. Basic SPC practices like plotting control charts will not, by themselves, improve yields; the control charts are, however, among the necessary tools used in the determination of the process capability and in the formulation of the problems to be addressed. The example we shall consider is the twofold objective of shifting the process average, while tightening the variance, of polysilicon line widths. This goal was identified from a Pareto analysis of yield-limiting mechanisms, plus inspection of the control charts. A key issue in a characterization of this type of process is the number of interactions between variables; this example rules out two-level full factorial and three-level fractional factorial designs (which cannot detect all of the interactions). We arrive at an experiment with five factors at five levels each. A full factorial design for five factors at three levels would require 3125 wafers. Instead, we will use a design that allows us to run this experiment with only 25 wafers, for a significant reduction in time, materials and manufacturing interruption in order to complete the experiment. An optimum solution is then determined via response surface analysis and a series of 3-D and contour plots are shown. The offset between the mask dimensions and poly CD at the optimum operating conditions is discussed with respect to yield, profits and return-on-investment. The expert system used for process optimization covers all types of process steps, producing the best custom designed experiment based on the actual equipment used. The knowledge base contains parameter lists, by machine make and model, ranked by sensitivity and controllability. One option allows 3-D spatial characterization of equipment. For the purpose of this presentation, we will assume that we want to optimize a photo-lithographic process used for polysilicon pattern definition and that we have determined minimum and maximum line widths, based on electrical yield requirements of the product. For this MOS process, the minimum critical dimension (CD) for the poly gate was determined by punchthrough voltage, threshold voltage, etc., while the maximum CD was determined from other performance factors like access time. We will start with the product engineer's analysis.

Expert systems for photolithography or photolithography-related domains are being built by many semiconductor chip manufacturers, fabrication equipment manufacturers, and university groups. This paper describes several such applications for process control, diagnosis, automation, design, simulation, planning, and scheduling. Benefits and implementation issues are highlighted.

This paper describes a test chip, test results, rule generation techniques, and an expert system for characterizing the performance of a sub-micron lithography process. Examples of test results, data reduction techniques, and expert system output are given. The objective of this work is to develop a system for automatic process diagnosis.

A hierarchical analysis of variance is combined with statistical process control to analyze production linewidth data. The analysis produces estimates of measurement errors, lot to lot variation, within lot variation, and the magnitude of the different contributions to variation. In all cases, the results from multiple lots are tested to see if the process is in "statistical control". The errors associated with centering the process, with respect to device specifications, are also calculated. The total variation of the lines is compared to the device specifications to determine process capability. An example of the analysis, with some data from the AZ Sunnyvale Applications Laboratory, is shown.

In a trilevel resist system, the thick polymer planarizing layer serves as the masking layer for pattern transfer to the substrate. This paper addresses the problems of achieving accurate pattern transfer to the planarizing layer. As in every Reactive Ion Etch (RIE) step, linewidth changes should be minimized in order to achieve faithful representation of the lithographic pattern. Linewidth loss can take place during the pattern transfer to the intermediate layer because of excessive resist erosion, due to erosion of the intermediate layer during pattern transfer to the planarizing layer, and due to lateral etch of the planarizing layer during its definition. As critical dimensions decrease below 1 tan and device density increases, proximity may affect line shape and width too. Methods to minimize linewidth changes due to the above mechanisms are discussed; specifically, the advantages of using carbon-dioxide for the planarizing layer etch are presented.