Share Email Print

Proceedings Paper

Circulating Packet Threshold Logic To Implement Msd Logic Modules
Author(s): David L. Flannery; L. Maugh Vail; Steven C. Gustafson
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Threshold logic element designs in circulating packet form are presented for the implementation of addition and subtraction using modified sign digit (MSD) arithmetic. This arithmetic is attractive for digital optical computing due to its inherent parallelism and pipelining characteristics, which capitalize on natural strengths of optics. To illustrate application of these concepts, a design for CORDIC rotation modules to accomplish the complex Givens rotations required for systolic array QU matrix factorization is presented. This design accomplishes QU factorization using only threshold logic elements and bit-shift operations in a systolic configuration. Although implementable in principle by either electronic or optical means, the design is amenable to optical implementation because it involves high levels of parallelism and interconnections.

Paper Details

Date Published: 23 March 1986
PDF: 13 pages
Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976271
Show Author Affiliations
David L. Flannery, University of Dayton Research Institute (United States)
L. Maugh Vail, University of Dayton Research Institute (United States)
Steven C. Gustafson, University of Dayton Research Institute (United States)

Published in SPIE Proceedings Vol. 0698:
Real-Time Signal Processing IX
William J. Miceli, Editor(s)

© SPIE. Terms of Use
Back to Top