Proceedings Paper
Design And Vlsi Implementation Of An On-Line Algorithm| Format | Member Price | Non-Member Price |
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Paper Abstract
We present a design and its VLSI implementation of a radix-2 on-line algorithm for the basic function Y = AX + B in NMOS technology and discuss its area/time characteristics. The design uses internal pipelining to achieve a short step time of about three gate delays. The on-line delay is 5. The implementation is modular using a 150-transistor bit-slices. We also illustrate the use of the module in implementing a root solver for a polynomial equation.
Paper Details
Date Published: 23 March 1986
PDF: 8 pages
Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976250
Published in SPIE Proceedings Vol. 0698:
Real-Time Signal Processing IX
William J. Miceli, Editor(s)
PDF: 8 pages
Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976250
Show Author Affiliations
Dean M. Tullsen, University of California (United States)
Milos D. Ercegovac, University of California (United States)
Published in SPIE Proceedings Vol. 0698:
Real-Time Signal Processing IX
William J. Miceli, Editor(s)
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