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Proceedings Paper

Architectures For A Cordic SVD Processor
Author(s): Joseph R. Cavallaro; Franklin T. Luk
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Paper Abstract

Architectures for systolic array processor elements for calculating the singular value decomposition (SVD) are proposed. These special purpose VLSI structures incorporate the coordinate rotation (coRDic) algorithms to diagonalize 2X 2 submatrices of a large array. The area-time complexity of the proposed architectures is analyzed along with topics related to a prototype implementation.

Paper Details

Date Published: 23 March 1986
PDF: 9 pages
Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976245
Show Author Affiliations
Joseph R. Cavallaro, Cornell University (United States)
Franklin T. Luk, Cornell University (United States)

Published in SPIE Proceedings Vol. 0698:
Real-Time Signal Processing IX
William J. Miceli, Editor(s)

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