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Proceedings Paper

Evaluation Of Multilayer Resists For Submicron Technology
Author(s): Christoph Nolscher; Gunter Czech; Jurgen Karl; Klaus Koller
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Paper Abstract

PCM-, trilevel-RIE- and singlelevel-RIE-resist systems are investigated for application in submicron technology. Simulation results of the PCM-technique are compared with experimental results using the K809/PMMA system. Gate and sub-micron contact hole etch results are presented for the Shipley PCM system using PMGI as the planarizing layer. For the trilevel technique using SOG or a-Si as intermediate layer, the loss of linewidth during bottom resist 02-RIE was of main interest. Finally, a dry developing technique, the DESIRE process using the PLASMASK resist, was studied and tested on device wafers.

Paper Details

Date Published: 1 January 1988
PDF: 9 pages
Proc. SPIE 0920, Advances in Resist Technology and Processing V, (1 January 1988); doi: 10.1117/12.968345
Show Author Affiliations
Christoph Nolscher, Siemens Research Laboratory (Germany)
Gunter Czech, Siemens Research Laboratory (Germany)
Jurgen Karl, Siemens Research Laboratory (Germany)
Klaus Koller, Siemens Research Laboratory (Germany)

Published in SPIE Proceedings Vol. 0920:
Advances in Resist Technology and Processing V
Scott A. MacDonald, Editor(s)

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