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Proceedings Paper

Integrated Optical Pipeline Processor
Author(s): R. P. Kenan; C. M. Verber
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Paper Abstract

A pipelined processor is characterized by the use of multiple processors, each programmed to perform a specific part of an overall computing task. The task is typically broken down into segments that are conveniently performed as a unit, but which must be completed before the next segment is started. Such computational units, placed sequentially so as to perform the computing task, comprise the pipeline. Data and input parameters are provided to each computing unit as needed, externally from the system memory or internally from the preceding unit. To help control the flow of data and results, the pipeline is often run synchronously, with one output from each unit occurring each i time units. Units which complete their tasks in less time must wait for the other units to finish. This favors the use of systolic pipelines, as proposed by Kungl.

Paper Details

Date Published: 13 February 1986
PDF: 16 pages
Proc. SPIE 0634, Optical and Hybrid Computing, (13 February 1986); doi: 10.1117/12.964027
Show Author Affiliations
R. P. Kenan, Battelle Columbus Laboratory (United States)
C. M. Verber, Battelle Columbus Laboratory (United States)

Published in SPIE Proceedings Vol. 0634:
Optical and Hybrid Computing
Harold H. Szu, Editor(s)

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