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Proceedings Paper

Reduction Of Proximity Reflective Notching On A Double Metal Vlsi Process By High Temperature Post Exposure Baked
Author(s): John L. Nistler; Tom R. Mead; Mark A. Spak
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Paper Abstract

An alternative to bilevel and trilevel photolithography for 1.5 μm double metal VLSI processes is presented. It is accomplished by a single level resist process that uses AZ4210D dyed resist and high temperature post exposure bake. Scanning electron micrographs show that proximity reflective notching and linewidth variation across topography steps on a double metal production process can be virtually eliminated. We have been able to confirm, via SEM analysis, an enhanced diffusion mechanism of the photosensitizer in the temperature range of 130° to 140°C. Quantitative data comparing relective notching versus linewidth as a function of process parameters is presented. Though not presented, we have shown that the HTPEB single level resist process does not reduce throughput in our fabrication area. It is achievable using either track or batch develop techniques.

Paper Details

Date Published: 9 July 1986
PDF: 9 pages
Proc. SPIE 0631, Advances in Resist Technology and Processing III, (9 July 1986); doi: 10.1117/12.963645
Show Author Affiliations
John L. Nistler, VTC Incorporated (United States)
Tom R. Mead, VTC Incorporated (United States)
Mark A. Spak, AZ Photoresist Products (United States)

Published in SPIE Proceedings Vol. 0631:
Advances in Resist Technology and Processing III
C. Grant Willson, Editor(s)

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