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Proceedings Paper

Development Of A High-Speed TV Digitizer
Author(s): H. Shimoda; I. Fujitaka; T. Sakata; K. Fukue
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Paper Abstract

A high-speed TV digitizing system was developed. It consists of a high-resolution vidicon camera, a read-out controller, a video densitometer which is an A/D conversion unit (VDM), a video RAM and its controller, and a shading correction system. Control command bus lines connect the CPU (HP 2113-E), TV camera, read-out controller, shading corrector, and video RAM controller, while digitized data from the VDM are written directly into the video RAM which can be accessed from the CPU through DMA channel. The TV camera used was a Hamamatsu C-1000 vidicon camera which has about 1000 x 1000 resolution elements by 1:4 interlace. Sixteen-point sampling for each scan line was achieved by this configuration in spite of the use of the relatively slow combination of sample and hold circuit and A/D conver-ter, which has 3 µsec access time. Digitizing period for whole frames was about 1.1 sec. for 512 x 512 samplings under 2:1 interlace ratio, with 8 bit accuracy. Further, a combination of an analogue and a digital shading corrector controlled by the CPU enabled a real-time and flexible shading correction.

Paper Details

Date Published: 27 July 1979
PDF: 4 pages
Proc. SPIE 0189, 13th Intl Congress on High Speed Photography and Photonics, (27 July 1979);
Show Author Affiliations
H. Shimoda, Tokai University (Japan)
I. Fujitaka, Tokai University (Japan)
T. Sakata, Tokai University (Japan)
K. Fukue, Tokai University (Japan)

Published in SPIE Proceedings Vol. 0189:
13th Intl Congress on High Speed Photography and Photonics
Shin-Ichi Hyodo, Editor(s)

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