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Proceedings Paper

Flow-Form Implementation Of A Linear Predictive Coder For Speech Communication
Author(s): G. S. Kang; L. J. Fransen; E. L. Kline
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Paper Abstract

A number of real-time linear predictive coders ( LPCs) have been developed to compress speech waveforms to 2400 bits per second (bps). Most of these LPCs employ a central processing unit (CPU) to analyze a stream of speech samples on a frame-by-frame (block-form) basis. While physical size, weight and power dissipation of these units have been decreasing steadily, the operation of a battery-powered hand-carried unit is far from realization. This paper presents the flow-form implementation of an LPC as an alternative to the block-form CPU intensive approach. The flow-form implementation of an LPC allows for decentralized, semi-autonomous, arithmetic-intensive segments which are supplemented by a microprocessor. The microprocessor performs relatively non-taxing logic operations and computations. F low-form analysis computation is highly systematic and repetitive making this form of analysis well-suited for Very Large Scale Integration (VLSI). Because flow-form analysis does not require a large array of stored data, less data memory is required and power dissipation is reduced. With current technology an LPC can be implemented using fewer than ten chips and having a total power dissipation of less than three watts. The flow-form LPC is comparable in performance to the block-form LPC, and the two units are interoperable, provided the same coding rules and data transmission formats are used.

Paper Details

Date Published: 21 September 1979
PDF: 10 pages
Proc. SPIE 0180, Real-Time Signal Processing II, (21 September 1979); doi: 10.1117/12.957308
Show Author Affiliations
G. S. Kang, Naval Research Laboratory (United States)
L. J. Fransen, Naval Research Laboratory (United States)
E. L. Kline, Naval Research Laboratory (United States)

Published in SPIE Proceedings Vol. 0180:
Real-Time Signal Processing II
Tien F. Tao, Editor(s)

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