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Proceedings Paper

Charge-Coupled Device Pinning Technologies
Author(s): James Janesick; Tom Elliott; George Frasehetti; Stewart Collins; Morley Blouke; Brian Corrie
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Paper Abstract

For most thinned silicon CCDs, the photosensitive volume is bounded on top and bottom by layers of silicon dioxide. The frontside oxide is grown to serve as an insulator beneath the conductive gates of the parallel array while the backside oxide forms naturally as the initially bare silicon oxidizes. This paper describes the characteristics of the interface between these oxides and the photo-sensitive silicon and indicates the extent to which CCD performance (e.g. dark current, spectral response, charge collection efficiency, charge transfer efficiency, pixel-nonuniformity read noise full well capacity blooming residual image and vulnerability to ionizing radiation damage) depend* upon these interfacial characteristics. Techniques are described to achieve optimum passivation of these interfaces and to thereby obtain superior performance in the areas just listed. Specifically an implanted structure (the Multi-Pinned-Phase, MPP) is described which provides excellent frontside passivation and several techniques (backside charging, flash gate, the biased flash gate and ion-implantation) are presented for back surface passivation.

Paper Details

Date Published: 23 May 1989
PDF: 17 pages
Proc. SPIE 1071, Optical Sensors and Electronic Photography, (23 May 1989); doi: 10.1117/12.952516
Show Author Affiliations
James Janesick, California Institute of Technology (United States)
Tom Elliott, California Institute of Technology (United States)
George Frasehetti, California Institute of Technology (United States)
Stewart Collins, California Institute of Technology (United States)
Morley Blouke, Tektronix Incorporated (United States)
Brian Corrie, Tektronix Incorporated (United States)

Published in SPIE Proceedings Vol. 1071:
Optical Sensors and Electronic Photography
Morley M. Blouke; Donald Pophal, Editor(s)

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