Because it is nearly impossible with todays technology to make a processor which is optimised for all possible image processing tasks one tries to realize different processors each of them being a compromise between technology, processing speed and class of operations that must be performed optimaly. This paper describes a hardware module to be part of a general image computer that is being developed in our laboratory. The design of this single board module was started to provide us with a flexible and high speed processor reprogrammable for several classes of image operations. To some extend this processor will be useful in hierarchical structures which seem to be very promising concepts at our days.

Date Published: 21 April 1986
PDF: 9 pages
Proc. SPIE 0596, Architectures and Algorithms for Digital Image Processing III, (21 April 1986); doi: 10.1117/12.952289

Published in SPIE Proceedings Vol. 0596:
Architectures and Algorithms for Digital Image Processing III
Francis J. Corbett; Howard Jay Siegel; Michael J. Duff, Editor(s)