An architecture and alforithms for a VLSI computer for back-projection image reconstruction are described. The computer consists of multiple identical back-projection processors connected in a linear array. Image pixels are pumped through the processor array, collecting at each processor a contribution to the image from one of its projections. Given one back-projection processor for each image projection, the entire reconstruction can be performed in a time comparable to that needed for sequential access of all image pixels. Implementation of a MOS VLSI back-projection processor is well advanced with working designs obtained for most processor subsystems. The processor incorporates a linear interpolator to estimate values between projection samples and accommodates non-linearity in the geometrical relationship between an image and its projection.

Date Published: 21 April 1986
PDF: 6 pages
Proc. SPIE 0596, Architectures and Algorithms for Digital Image Processing III, (21 April 1986); doi: 10.1117/12.952283

Published in SPIE Proceedings Vol. 0596:
Architectures and Algorithms for Digital Image Processing III
Francis J. Corbett; Howard Jay Siegel; Michael J. Duff, Editor(s)