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Proceedings Paper

Digital-Analog-Hybrid Neural Simulator: A Design-Aid For Custom-VLSI Neurochips
Author(s): A. Moopenn; A. P. Thakoor; T. Duong
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Paper Abstract

A high speed neural network simulator and its use for the dynamics and performance analysis of feedback neural architectures are described. The simulator is based on a semi-parallel, analog-digital hybrid architecture which utilizes digital memories to store synaptic weights and analog hardware for high speed computation. A breadboard system with 8-bit gray scale synapses, designed and built at JPL, is successfully serving as a valuable design test-bed for the development of fully parallel, analog, custom VLSI neurochips, currently underway at JPL. The breadboard hybrid simulator indeed allows a detailed evaluation of hardware potential and limitations in implementing full analog operations in such chips. As an example, the paper presents an analysis of the stability and convergence behavior of a feedback neural network applied to the "Concentrator Assignment Problem" in combinatorial optimization, as studied on the analog-digital hybrid simulator. This has already resulted in a VLSI custom design of a fully parallel, analog neuroprocessor with a powerful "analog prompting" feature, for the high-speed, multiparameter optimization function.

Paper Details

Date Published: 17 May 1989
PDF: 11 pages
Proc. SPIE 1058, High Speed Computing II, (17 May 1989); doi: 10.1117/12.951677
Show Author Affiliations
A. Moopenn, California Institute of Technology (United States)
A. P. Thakoor, California Institute of Technology (United States)
T. Duong, California Institute of Technology (United States)

Published in SPIE Proceedings Vol. 1058:
High Speed Computing II
Keith Bromley, Editor(s)

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