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Proceedings Paper

Parallel Recirculating Pipeline For Signal And Image Processing
Author(s): Bill Wehner
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Paper Abstract

Current image analysis and image understanding applications in DoD systems require very high performance image pixel processing in real time. To attain the necessary performance within stringent system size, weight, and power constraints requires special-purpose parallel processing hardware architectures. At the same time, it is desirable to retain as much programmability as possible in order to rapidly adapt the hardware to new applications or evolving system requirements. The Parallel Recirculating Pipeline processor uses techniques adopted from image algebra and mathematical morphology to provide a low-cost, low-complexity, high-performance architecture that is suitable for silicon implementation and programmable in high-order languages.

Paper Details

Date Published: 17 May 1989
PDF: 7 pages
Proc. SPIE 1058, High Speed Computing II, (17 May 1989); doi: 10.1117/12.951663
Show Author Affiliations
Bill Wehner, Honeywell Systems & Research Center (United States)

Published in SPIE Proceedings Vol. 1058:
High Speed Computing II
Keith Bromley, Editor(s)

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