Proceedings PaperParallel Recirculating Pipeline For Signal And Image Processing
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Current image analysis and image understanding applications in DoD systems require very high performance image pixel processing in real time. To attain the necessary performance within stringent system size, weight, and power constraints requires special-purpose parallel processing hardware architectures. At the same time, it is desirable to retain as much programmability as possible in order to rapidly adapt the hardware to new applications or evolving system requirements. The Parallel Recirculating Pipeline processor uses techniques adopted from image algebra and mathematical morphology to provide a low-cost, low-complexity, high-performance architecture that is suitable for silicon implementation and programmable in high-order languages.