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Proceedings Paper

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Author(s): Edmond S. Cooley; Scott J. Israel
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Paper Abstract

Novel circuitry that logarithmically reduces the number of adder delays needed for converting mixed binary to true binary is introduced. This circuitry, which has been built with standard TTL parts, can be easily improved using high speed VLSI CMOS, thereby increasing the overall efficiency of multiplier/converter modules.

Paper Details

Date Published: 4 January 1986
PDF: 3 pages
Proc. SPIE 0564, Real-Time Signal Processing VIII, (4 January 1986); doi: 10.1117/12.949710
Show Author Affiliations
Edmond S. Cooley, Dartmouth College (United States)
Scott J. Israel, Aerodyne Research, Inc. (United States)

Published in SPIE Proceedings Vol. 0564:
Real-Time Signal Processing VIII
Keith Bromley; William J. Miceli, Editor(s)

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