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Proceedings Paper

High Resolution, High Precision I-Line Stepper Processing
Author(s): H. Yanazawa; N. Hasegawa; T. Kurosaki; N. Hashimoto; S. Nonogaki
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Paper Abstract

Currently, the integrated MOS dynamic RAM has as many as 256 thousand memory cells per chip based on 2 pm photolithography. Figure 1 shows the history and the prospects for progress in microfabrication technology. Feature size versus year, as reported by Bossung in 1978, is shown, as developed from independent analysis by Moore, Noyce and Gnostic concept. Circles numbered 1 and 2 show that 64K- and 256K-bit RAMs were developed in 1981 and 1984, and that their feature sizes were 3μm and 2μm, respectively. It is significant that the predictions and the real developments are so close. Furthermore, since the basic process for 3 M-bit RAMs based on 1.3μm microlithography has already been reported in conference, it is highly likely that they will become commercially available around 1987, as predicted by the circle numbered 3 based on 1.3μm microlithography.

Paper Details

Date Published: 20 June 1985
PDF: 6 pages
Proc. SPIE 0537, Electron-Beam, X-Ray, and Ion-Beam Techniques for Submicrometer Lithographies IV, (20 June 1985); doi: 10.1117/12.947496
Show Author Affiliations
H. Yanazawa, Hitachi Ltd. (Japan)
N. Hasegawa, Hitachi Ltd. (Japan)
T. Kurosaki, Hitachi Ltd. (Japan)
N. Hashimoto, Hitachi Ltd. (Japan)
S. Nonogaki, Hitachi Ltd. (Japan)

Published in SPIE Proceedings Vol. 0537:
Electron-Beam, X-Ray, and Ion-Beam Techniques for Submicrometer Lithographies IV
Phillip D. Blais, Editor(s)

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