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Proceedings Paper

Multilevel Interconnects For Integrated Circuits With Submicron Design Rules
Author(s): S. R. Wilson; R. J. Mattox; J. Seeger
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Paper Abstract

A number of advanced processing tools and techniques have been used to demonstrate a multilevel metal interconnect module for VLSI circuits with <1µm design rules. A Perkin Elmer AEBLE 150 e-beam lithography tool has been used to print features with a range of dimensions as small as 0.5μm. These results are compared to those obtained on an ULTRATECH model 1000 1X stepper. Multilevel masking techniques plus dry etching have been used to ensure vertical feature walls and to reduce the loss of critical dimensions during the pattern transfer process. In order to completely fill contacts and vias, chemical vapor deposited tungsten (CVD W) was used in conjunction with a TiW barrier between the W and the silicon/silicide in the contact openings. To lower the interconnect resistance, aluminum alloy films (AlTi(0.2%) or AlCu(1.5%)) have been sputter deposited on top of the W film. In some cases where first metal resistance is not a critical issue, 0.45μm of CVD W without Al on top has been used as a metal film. Low temperature deposited oxides (both doped and undoped) have been used in conjunction with spin-on-glass (SOG) and etchback techniques to form partially planar ILD structures. Test structures fabricated using these processes have been examined with electrical testing and physical analysis.

Paper Details

Date Published: 16 August 1988
PDF: 9 pages
Proc. SPIE 0945, Advanced Processing of Semiconductor Devices II, (16 August 1988); doi: 10.1117/12.947384
Show Author Affiliations
S. R. Wilson, Bipolar Technology Center (United States)
R. J. Mattox, Bipolar Technology Center (United States)
J. Seeger, Bipolar Technology Center (United States)

Published in SPIE Proceedings Vol. 0945:
Advanced Processing of Semiconductor Devices II
Harold G. Craighead; Jagdish Narayan, Editor(s)

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