Proceedings Paper
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Paper Abstract
The design of a high-speed (250 million 32-bit floating point operations per second) two dimensional systolic array composed of 16 bit/slice microsequencer structured processors will be presented. System design features such as broadcast data flow, tag bit movement, and integrated diagnostic test registers will be described. The software development tools needed to map complex matrix-based signal processing algorithms onto the systolic processor system will be described.
Paper Details
Date Published: 25 November 1987
PDF: 10 pages
Proc. SPIE 0827, Real-Time Signal Processing X, (25 November 1987); doi: 10.1117/12.942052
Published in SPIE Proceedings Vol. 0827:
Real-Time Signal Processing X
J. P. Letellier, Editor(s)
PDF: 10 pages
Proc. SPIE 0827, Real-Time Signal Processing X, (25 November 1987); doi: 10.1117/12.942052
Show Author Affiliations
Joseph P. Loughlin, Naval Ocean Systems Center (United States)
Published in SPIE Proceedings Vol. 0827:
Real-Time Signal Processing X
J. P. Letellier, Editor(s)
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