
Proceedings Paper
Linewidth Control In Trilevel EtchingFormat | Member Price | Non-Member Price |
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Paper Abstract
In a trilevel resist system, the thick polymer planarizing layer serves as the masking layer for pattern transfer to the substrate. This paper addresses the problems of achieving accurate pattern transfer to the planarizing layer. As in every Reactive Ion Etch (RIE) step, linewidth changes should be minimized in order to achieve faithful representation of the lithographic pattern. Linewidth loss can take place during the pattern transfer to the intermediate layer because of excessive resist erosion, due to erosion of the intermediate layer during pattern transfer to the planarizing layer, and due to lateral etch of the planarizing layer during its definition. As critical dimensions decrease below 1 tan and device density increases, proximity may affect line shape and width too. Methods to minimize linewidth changes due to the above mechanisms are discussed; specifically, the advantages of using carbon-dioxide for the planarizing layer etch are presented.
Paper Details
Date Published: 17 April 1987
PDF: 7 pages
Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); doi: 10.1117/12.940441
Published in SPIE Proceedings Vol. 0775:
Integrated Circuit Metrology, Inspection, & Process Control
Kevin M. Monahan, Editor(s)
PDF: 7 pages
Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); doi: 10.1117/12.940441
Show Author Affiliations
Avi Kornblit, AT&T Bell Laboratories (United States)
Michael J. Grieco, AT&T Bell Laboratories (United States)
Michael J. Grieco, AT&T Bell Laboratories (United States)
Darryl W. Peters, AT&T Bell Laboratories (United States)
Thomas E. Saunders, AT&T Bell Laboratories (United States)
Thomas E. Saunders, AT&T Bell Laboratories (United States)
Published in SPIE Proceedings Vol. 0775:
Integrated Circuit Metrology, Inspection, & Process Control
Kevin M. Monahan, Editor(s)
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