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Proceedings Paper

Electrical And SEM Metrology Analyses Of Pattern Dimension Accuracy And Process Control In Direct Write Electron Beam Lithography
Author(s): Rao M. Nagarajan; Brian R. Lee; Steven D. Rask
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Paper Abstract

In this paper, state-of-the-art integrated circuit micrometrology techniques are described for linewidth control measurements and process control/repeatability of the image reversal process of photoresist AZ1470 by direct-write electron beam lithography. The micrometrology measurements involve electrical (Prometrix) and electron-optical (SEM) methods applied to submicron CMOS prototype VLSI circuits. Results obtained by these metrology techniques are presented and compared. The electron beam direct writer is a Cambridge EBMF6.5 system vector scan electron beam machine capable of achieving ultrahigh current densities with a beam of circular cross section and a gaussian intensity profile operated at 20 kev. The etched pattern linewidth accuracy for this electron beam lithography system is determined by errors related to: (a) resist-process, (b) e-beam machine and (c) proximity effect. This paper mainly deals with the analysis of such resist-process related errors, though machine related and proximity effect related errors are also discussed. The resist-process related errors stem from five sources: 1) soft bake temperature effect, 2) e-beam exposure dose, 3) ultraviolet flood exposure dose, 4) development processing and 5) etching uniformity. We have made separate determination of each error through critical dimension control measurements. It was found that e-beam dose, and development processes contributed the most to the process related errors. Our results show that there is close agreement between the electrical and SEM measurements within the accuracy of each technique. This image reversal process consistently produces critical dimension uniformity of one sigma (la) values of about 0.05μm. The linewidths are controlled within 10%. Thus, the results from the metrology data indicate that this resist process can be used to fabricate 0.5μm polysilicon gate structures (although isolated polygate features as small as 0.25μm can be achieved).

Paper Details

Date Published: 17 April 1987
PDF: 8 pages
Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); doi: 10.1117/12.940429
Show Author Affiliations
Rao M. Nagarajan, UNISYS Corporation (United States)
Brian R. Lee, UNISYS Corporation (United States)
Steven D. Rask, UNISYS Corporation (United States)

Published in SPIE Proceedings Vol. 0775:
Integrated Circuit Metrology, Inspection, & Process Control
Kevin M. Monahan, Editor(s)

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