The diminishing size of VLSI features necessitates the use of a scanning electron microscope (SEM) for making inprocess CD measurements. The intent of this paper is to establish a methodology for improving the accuracy and precision of such measurements. In SEM metrology, the challenge lies in determining two points in the secondary electron line-scan corresponding to the feature edges. The systematic errors introduced by incorrect edge detection can be reduced greatly by optimizing the linescan with proper choice of SEM operating conditions. Experiments on two samples of interest in VLSI processing demonstrate the advantage of increased accelerating voltage for minimizing measuremental uncertainty. In addition, measuremental robustness, or sensitivity of linewidth measurement to SEM defocus, is shown to be strongly dependent upon the specific edge detection algorithm used.

Date Published: 17 April 1987
PDF: 7 pages
Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); doi: 10.1117/12.940423

Published in SPIE Proceedings Vol. 0775:
Integrated Circuit Metrology, Inspection, & Process Control
Kevin M. Monahan, Editor(s)