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Proceedings Paper

Comparison Of Exposure Latitude For Single Layer Resist Processes
Author(s): Larry D. Hutchins
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Paper Abstract

One of the critical processes in the fabrication of state-of-the-art VLSI MOS circuits is the polysilicon gate photolithography. The combination of near-micron or submicron design rules, substrate topography and substrate reflectivity imposes stringent requirements on the performance and latitude of the photopatterning process. Numerous techniques have been developed to enhance the performance of photolithographic processes, including the use of Multi-Layer Resist systems,1-4 Anti-Reflective Coatings,19996 Contrast Enhancement Layers,1,7 dyed resists,199 and Post-Exposure Bakes (PEB).9-11 Of primary concern is the control of resist feature critical dimensions (CDs). Control of CDs to within ± 10% of the nominal value is typically desired. Although many parameters have an effect on resist CDs, the major factor is usually the exposure dose. This study was undertaken in an effort to characterize the resist CD latitude as a function of exposure dose for four key Single Layer Resist processes: (1) Kodak 820 resist; (2) Kodak 820 resist with PEB; (3) dyed Kodak 820 resist; and (4) dyed Kodak 820 resist with PEB.

Paper Details

Date Published: 17 April 1987
PDF: 6 pages
Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); doi: 10.1117/12.940408
Show Author Affiliations
Larry D. Hutchins, Unisys Corporation (United States)

Published in SPIE Proceedings Vol. 0775:
Integrated Circuit Metrology, Inspection, & Process Control
Kevin M. Monahan, Editor(s)

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