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Proceedings Paper

Image Processing System With Time Shared Multiframe Data Bus Architecture: MFIP
Author(s): S. Sugimoto; K. Matsuoka; Y. Ichioka
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Paper Abstract

A general purpose, high-speed image processing system with a time shared multiframe data bus architecture and with multi-processors--MFIP--has been developed. Massive image data can be transferred from/to multiple memory modules to/from multi-processors through the high-speed time shared multiframe data bus (40 MW/sec). The system is built up, centering on 2MW large image memory consisting of eight memory modules with 256KW (1W = 16 bits). Image memory can be expanded up to 8MW, i.e., 32 memory modules. This paper describes the gross architecture of MFIP, and functional and operational features of the high-speed time shared multiframe data bus. Then design concept and manufacture of two image processing units, A and B in the system are presented.

Paper Details

Date Published: 9 January 1984
PDF: 8 pages
Proc. SPIE 0435, Architectures and Algorithms for Digital Image Processing, (9 January 1984); doi: 10.1117/12.937007
Show Author Affiliations
S. Sugimoto, Osaka University (Japan)
K. Matsuoka, Osaka University (Japan)
Y. Ichioka, Osaka University (Japan)

Published in SPIE Proceedings Vol. 0435:
Architectures and Algorithms for Digital Image Processing
Per-Erik Danielsson; Andre J. Oosterlinck, Editor(s)

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