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Proceedings Paper

A One Gigaflop VLSI Systolic Processor
Author(s): John H. Avila; Philip J. Kuekes
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Paper Abstract

Inexpensive, efficient VLSI circuits combined with a highly parallel systolic architecture will allow the construction of one gigaflop linear algebra processors for signal processing. This paper presents some results in increasing the efficiency of such processors to 100%.

Paper Details

Date Published: 28 November 1983
PDF: 7 pages
Proc. SPIE 0431, Real-Time Signal Processing VI, (28 November 1983); doi: 10.1117/12.936454
Show Author Affiliations
John H. Avila, ESL Incorporated (United States)
Philip J. Kuekes, ESL Incorporated (United States)

Published in SPIE Proceedings Vol. 0431:
Real-Time Signal Processing VI
Keith Bromley, Editor(s)

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