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Proceedings Paper

Metal Oxide Semiconductor (MOS) Technology Scaling Issues And Their Relation To Submicron Lithography
Author(s): Al F. Tasch Jr.
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Paper Abstract

This paper examines the impact of submicron MOS integrated circuit technology on submicron lithography, and contrasts the lithography picture today with that for submicron features. A considerably larger number of factors must be dealt with rigorously because they either do not scale with decreasing dimensions or they do not lend themselves easily to more rigid control so that it has become disproportionately difficult to reduce their effect. In addition to the lithography issues, other serious device technology limitations arise at submicron dimensions. These have to do with device isolation, gate insulation, parasitic resistance and capacitance, interconnectivity, particle-induced upset, and hot electron effects. These issues must also be successfully resolved if submicron dimensions are to be successfully exploited in submicron integrated circuits.

Paper Details

Date Published: 30 June 1982
PDF: 8 pages
Proc. SPIE 0333, Submicron Lithography I, (30 June 1982); doi: 10.1117/12.933414
Show Author Affiliations
Al F. Tasch Jr., Texas Instruments Incorporated (United States)

Published in SPIE Proceedings Vol. 0333:
Submicron Lithography I
Phillip D. Blais, Editor(s)

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