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Proceedings Paper

Processing Display System Architectures
Author(s): L. Howard Roberts; Michael Shantz
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Paper Abstract

Recent advances in the design of image processing and display equipment have occurred in two key areas, namely, data flow architectures and pipeline array processor architectures. Data flow involves the use of high speed data interfaces to the display processor, a flexible internal bus architecture, and efficient access to display processor memories. Image processing power is achieved through the use of pipeline processors rather than high-speed, large address-space, integral CPUs. Hardware constraints impact the design of algorithms which take advantage of the 70 nanosecond pixel rates and the computational power of the pipeline processors. The DeAnza Systems IP 8500 and IP 1172 image processing display systems exemplify architectural advances in data flow and pipeline processor architectures.

Paper Details

Date Published: 23 July 1982
PDF: 11 pages
Proc. SPIE 0301, Design of Digital Image Processing Systems, (23 July 1982); doi: 10.1117/12.932609
Show Author Affiliations
L. Howard Roberts, DeAnza Systems, Inc. (United States)
Michael Shantz, DeAnza Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 0301:
Design of Digital Image Processing Systems
James L. Mannos, Editor(s)

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