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Proceedings Paper

Semi-Analytical Estimation of Intra-Die Variations of Analog Performances of Nano-scale nMOS Transistor
Author(s): Sarmista Sengupta; Soumya Pandit
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Paper Abstract

This paper presents a semi analytical technique for estimating the effects of intra-die process variations on the performances of an nMOS transistor. The intra-die process variability sources considered in the work are Random Discrete Dopants (RDD), Channel Length Variation (CLV), Oxide Thickness Variation (OTV) and Mobility Fluctuation (MF). The analog performances which are studied are transconductance gm, intrinsic speed ft , thermal noise spectral density Sn and flicker noise spectral density Sf. The estimation technique is based on BSIMIV-SPICE process parameters. The mean and standard deviation of the performance variations are estimated. The estimated results are verified through Monte Carlo (MC)-HSPICE simulation results.

Paper Details

Date Published: 15 October 2012
PDF: 6 pages
Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 854904 (15 October 2012); doi: 10.1117/12.925339
Show Author Affiliations
Sarmista Sengupta, Univ. of Calcutta (India)
Soumya Pandit, Univ. of Calcutta (India)

Published in SPIE Proceedings Vol. 8549:
16th International Workshop on Physics of Semiconductor Devices
Monica Katiyar; B. Mazhari; Y N Mohapatra, Editor(s)

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