We present a bio-inspired system-on-chip focal plane readout architecture which at the system level, relies on an event based sampling scheme where only pixels within a programmable range of photon flux rates are output. At the pixel level, a one bit oversampled analog-to-digital converter together with a decimator allows for the quantization of signals up to 26 bits. Furthermore, digital non-uniformity correction of both gain and offset errors is applied at the pixel level prior to readout. We report test results for a prototype array fabricated in a standard 90nm CMOS process. Tests performed at room and cryogenic temperatures demonstrate the capability to operate at a temporal noise ratio as low as 1.5, an electron well capacity over 100Ge-, and an ADC LSB down to 1e-.

Date Published: 31 May 2012
PDF: 16 pages
Proc. SPIE 8353, Infrared Technology and Applications XXXVIII, 83531N (31 May 2012); doi: 10.1117/12.919584

Published in SPIE Proceedings Vol. 8353:
Infrared Technology and Applications XXXVIII
Bjørn F. Andresen; Gabor F. Fulop; Paul R. Norton, Editor(s)