
Proceedings Paper
High-order wafer alignment in manufacturingFormat | Member Price | Non-Member Price |
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Paper Abstract
Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC
processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of
overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and
unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and
linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment
cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes.
Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic
errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid
distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment
data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are
calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated.
How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and
matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This
evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product
specific corrections per exposure and 10 term APC process control.
Paper Details
Date Published: 4 April 2012
PDF: 11 pages
Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 832408 (4 April 2012); doi: 10.1117/12.916483
Published in SPIE Proceedings Vol. 8324:
Metrology, Inspection, and Process Control for Microlithography XXVI
Alexander Starikov, Editor(s)
PDF: 11 pages
Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 832408 (4 April 2012); doi: 10.1117/12.916483
Show Author Affiliations
Michael Pike, IBM Corp. (United States)
Nelson Felix, IBM Corp. (United States)
Vinayan Menon, IBM Corp. (United States)
Christopher Ausschnitt, IBM Corp. (United States)
Nelson Felix, IBM Corp. (United States)
Vinayan Menon, IBM Corp. (United States)
Christopher Ausschnitt, IBM Corp. (United States)
Timothy Wiltshire, IBM Corp. (United States)
Sheldon Meyers, GLOBALFOUNDRIES Inc. (United States)
Won Kim, ASML US, Inc. (United States)
Blandine Minghetti, ASML US, Inc. (United States)
Sheldon Meyers, GLOBALFOUNDRIES Inc. (United States)
Won Kim, ASML US, Inc. (United States)
Blandine Minghetti, ASML US, Inc. (United States)
Published in SPIE Proceedings Vol. 8324:
Metrology, Inspection, and Process Control for Microlithography XXVI
Alexander Starikov, Editor(s)
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