
Proceedings Paper
Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout designFormat | Member Price | Non-Member Price |
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Paper Abstract
This paper addresses the framework for building critical recommended rules and a methodology for devising scoring
models using simulation or silicon data. Recommended rules need to be applied to critical layout configurations (edge or
polygon based geometric relations), which can cause yield issues depending on layout context and process variability.
Determining of critical recommended rules is the first step for this framework. Based on process specifications and
design rule calculations, recommended rules are characterized by evaluating the manufacturability response to
improvements in a layout-dependent parameter. This study is applied to critical 20nm recommended rules. In order to
enable the scoring of layouts, this paper also discusses a CAD framework involved in supporting use-models for
improving the DFM-compliance of a physical design.
Paper Details
Date Published: 14 March 2012
PDF: 13 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270U (14 March 2012); doi: 10.1117/12.916288
Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)
PDF: 13 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270U (14 March 2012); doi: 10.1117/12.916288
Show Author Affiliations
Piyush Pathak, GLOBALFOUNDRIES Inc. (United States)
Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)
Shobhit Malik, GLOBALFOUNDRIES Inc. (United States)
Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)
Shobhit Malik, GLOBALFOUNDRIES Inc. (United States)
Lynn T.-N. Wang, GLOBALFOUNDRIES Inc. (United States)
Luigi Capodieci, GLOBALFOUNDRIES Inc. (United States)
Luigi Capodieci, GLOBALFOUNDRIES Inc. (United States)
Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)
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