Full chip verification has become a key component of the optical proximity correction (OPC) methodology over the last decade. Full field verification to catch cross-field effects based on scanner information is becoming increasingly important in lithography verification. Lithographic Manufacturing Check (LMC) performed with the Brion Tachyon engine, which is the industry reference tool, now provides the capability to predict wafer CD variations across the entire field through process windows. LMC is catching and reporting weak lithographic points having small process windows or excessive sensitivities to mask errors based on the simulation from models with ASML scanner specific parameters. ASML scanner intra-field information such as dose, focus, flare, illuminator map, aberration data or mask bias map can be integrated into the LMC run to create an across-field verification and can improve the accuracy of the prediction at different field locations. In this study we compare such across-field LMC verification with a reference LMC without any scanner specific data. Scanner information was loaded into the LMC model by using the Scanner Fingerprint File (SFF) functionality. Various across field LMC runs using scanner information have been performed and analysed to identify critical design hotspots or scanner drifts and compared with wafer measurement. Full field Tachyon LMC results on 40nm Poly and 28nm Metal1 layer are presented. The goal is to investigate the impact of mask, lens aberrations, illuminator, dose and focus map. This investigation includes wafer validation of the methodology on identified critical hot spots.

Date Published: 13 March 2012
PDF: 9 pages
Proc. SPIE 8326, Optical Microlithography XXV, 832617 (13 March 2012); doi: 10.1117/12.916151

Published in SPIE Proceedings Vol. 8326:
Optical Microlithography XXV
Will Conley, Editor(s)