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Proceedings Paper

Application of DBM system to overlay verification and wiggling quantification for advanced process
Author(s): Taehyeong Lee; Jungchan Kim; Gyun Yoo; Chanha Park; Hyunjo Yang; Donggyu Yim; Byoungjun Park; Kotaro Maruyama; Masahiro Yamamoto
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Paper Abstract

With the shrinkage of semiconductor device scales, advanced semiconductor industries face tremendous challenges in process control. As lithography and etch processes are pushed to get smaller dimensions, the overlay and wiggling control are hot issues due to the limiting of pattern performance. Many chip makers are using Double Patterning Technology (DPT) process to overcome design rule limitations but they are also concerned about overlay control. In DPT process, obtaining accurate overlay data by measuring overlay marks with traditional metrology is difficult because of the difference of shape and position between cell pattern and overlay marks. Cell to overlay mark miss-match will occur when there is lens aberration or mask registration error. Therefore, the best way to obtain accurate overlay data without error is to measure the real cell itself. The overlay of the cell array using DPT process can be measured by analyzing the relative position of the 2nd exposed pattern to the 1st exposed pattern. But it is not easy to clearly distinguish a 1st layer and 2nd layer in a patterned cell array image using CD SEM. The Design Based Metrology (DBM)-system can help identify which cell pattern is a 1st or 2nd layer, so overlay error between the 1st and 2nd layers at DPT process can be checked clearly. Another noticeable problem in advanced processing is wiggling. The wiggling of a pattern become severe by the etch process and must be controlled to meet electrical characteristics of what the semiconductor device requires. The 1st stage of wiggling control is to understand the level of wiggling which is crucial to device performance. The DBM-system also can be used for quantification of wiggling by determining specially designed parameters. In this paper we introduce overlay verification and wiggling quantification through new methodology for advanced memory devices.

Paper Details

Date Published: 5 April 2012
PDF: 9 pages
Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 83241B (5 April 2012); doi: 10.1117/12.916110
Show Author Affiliations
Taehyeong Lee, Hynix Semiconductor Inc. (Korea, Republic of)
Jungchan Kim, Hynix Semiconductor Inc. (Korea, Republic of)
Gyun Yoo, Hynix Semiconductor Inc. (Korea, Republic of)
Chanha Park, Hynix Semiconductor Inc. (Korea, Republic of)
Hyunjo Yang, Hynix Semiconductor Inc. (Korea, Republic of)
Donggyu Yim, Hynix Semiconductor Inc. (Korea, Republic of)
Byoungjun Park, Nano Geometry Research, Inc. (Japan)
Kotaro Maruyama, Nano Geometry Research, Inc. (Japan)
Masahiro Yamamoto, Nano Geometry Research, Inc. (Japan)

Published in SPIE Proceedings Vol. 8324:
Metrology, Inspection, and Process Control for Microlithography XXVI
Alexander Starikov, Editor(s)

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