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Proceedings Paper

Low-power integration of on-chip nanophotonic interconnect for high-performance optoelectrical IC
Author(s): Duo Ding; David Z. Pan
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Paper Abstract

In this manuscript we study the potentials of nanophotonics on-chip integration and propose a set of automation methodologies to construct low power on-chip interconnect with flexible geometry shapes. We show that with such techniques, a systematic design aid environment can be developed to generate optimized integration configurations meanwhile honoring complex sets of photonic device constraints. Due to their unique characteristics, not only do these techniques benefit the optimization of on-chip photonic networks, but also they can be efficiently applied to build low-power high-throughput application specific ICs with opto-electrical interconnection.

Paper Details

Date Published: 2 February 2012
PDF: 15 pages
Proc. SPIE 8267, Optoelectronic Interconnects XII, 82670Z (2 February 2012); doi: 10.1117/12.913886
Show Author Affiliations
Duo Ding, The Univ. of Texas at Austin (United States)
David Z. Pan, The Univ. of Texas at Austin (United States)

Published in SPIE Proceedings Vol. 8267:
Optoelectronic Interconnects XII
Alexei L. Glebov; Ray T. Chen, Editor(s)

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