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Proceedings Paper

A VLSI architecture for real-time signal FFT based on pipelined processing element
Author(s): Xu Wang; Yan Zhang; Jiannan Wang
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Paper Abstract

In this paper, a VLSI architecture for real-time signal FFT based on pipelined processing element (PE) is proposed. The proposed architecture suits to FFT/ IFFT and supports input/ output simultaneously. In the system a 2MN point FFT can be computed by 2M point row-wise FFT followed by 2N point column-wise 2-D FFT. By this way long length FFT is divided continuously until it could be conquered by some short length processing elements (PE). The proposed pipelined PE architectures are based on short length FFT algorithms used in WFTA, so multiplier number in PEs is minimal. A 1024-point complex FFT is implemented in XC2VP30-7 FPGA board based on the VLSI architecture. Result shows that latency between input and output is about 3300 clock cycles, and the computation time for real-time signal FFT is minimal compare to recent research. The proposed architecture also has flexible configuration for different point FFT.

Paper Details

Date Published: 1 October 2011
PDF: 9 pages
Proc. SPIE 8285, International Conference on Graphic and Image Processing (ICGIP 2011), 82855K (1 October 2011); doi: 10.1117/12.913420
Show Author Affiliations
Xu Wang, Harbin Institute of Technology (China)
Yan Zhang, Harbin Institute of Technology (China)
Jiannan Wang, Harbin Institute of Technology (China)


Published in SPIE Proceedings Vol. 8285:
International Conference on Graphic and Image Processing (ICGIP 2011)
Yi Xie; Yanjun Zheng, Editor(s)

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