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Proceedings Paper

Accelerating arithmetic coding on a graphic processing unit
Author(s): Liang Chen; Yong Fang; Bormin Huang
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Paper Abstract

The popularity of Graphic Processing Units (GPUs) opens a new avenue for general-purpose computation including the acceleration of algorithms. Massively parallel computations using GPUs have been applied in various fields by researchers. Arithmetic coding (AC) is widely used in lossless data compression and shows better compression efficiency than the well-known Huffman Coding. However, AC possesses much higher computational complexity due to frequent multiplication and branching operations. In this paper, we implement the block-parallel arithmetic encoder on GPUs using the NVIDIA GPU and the Computer Unified Device Architecture (CUDA) programming model. The source data sequence is divided into small blocks. Each CUDA thread processes one data block so that data blocks can be encoded in parallel. By exploiting the GPU computational power, a significant speedup is achieved. We show that the GPU-based AC speedup result depends on data distribution and size. It is observed that the GPU speedup increases with higher compression ratios, due to the fact that higher compression ratio corresponds to smaller compressed data output which reduces the bit stream concatenation time as well as the device-to-host transfer time. Applying to the selected test images in the USC-SIPI image database, we obtain speedup values ranging from 26x to 42x while compression ratios ranging from 1.4 to 2.7.

Paper Details

Date Published: 2 November 2011
PDF: 10 pages
Proc. SPIE 8183, High-Performance Computing in Remote Sensing, 81830B (2 November 2011); doi: 10.1117/12.897112
Show Author Affiliations
Liang Chen, Northwest A&F Univ. (China)
Yong Fang, Northwest A&F Univ. (China)
Bormin Huang, Univ. of Wisconsin-Madison (United States)

Published in SPIE Proceedings Vol. 8183:
High-Performance Computing in Remote Sensing
Bormin Huang; Antonio J. Plaza, Editor(s)

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