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Proceedings Paper

A high performance hardware implementation image encryption with AES algorithm
Author(s): Ali Farmani; Mohamad Jafari; Seyed Sohrab Miremadi
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Paper Abstract

This paper describes implementation of a high-speed encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES(Advanced Encryption Standard), in order to increase the speed and throughput using pipeline technique in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Such procedure makes AES suitable for fast image encryption. Implementation of a 128-bit AES on FPGA of Altra company has been done and the results are as follow: throughput, 6 Gbps in 471MHz. The time of encrypting in tested image with 32*32 size is 1.15ms.

Paper Details

Date Published: 8 July 2011
PDF: 7 pages
Proc. SPIE 8009, Third International Conference on Digital Image Processing (ICDIP 2011), 800905 (8 July 2011); doi: 10.1117/12.896659
Show Author Affiliations
Ali Farmani, Univ. of Tabriz (Iran, Islamic Republic of)
Mohamad Jafari, Univ. of Tabriz (Iran, Islamic Republic of)
Seyed Sohrab Miremadi, Univ. of Tabriz (Iran, Islamic Republic of)


Published in SPIE Proceedings Vol. 8009:
Third International Conference on Digital Image Processing (ICDIP 2011)
Ting Zhang, Editor(s)

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