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Proceedings Paper

3D interconnect metrology in CMS/ITRI
Author(s): Y. S. Ku; D. M. Shyu; W. T. Hsu; P. Y. Chang; Y. C. Chen; H. L. Pang
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Paper Abstract

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Paper Details

Date Published: 26 May 2011
PDF: 6 pages
Proc. SPIE 8082, Optical Measurement Systems for Industrial Inspection VII, 80820I (26 May 2011); doi: 10.1117/12.889401
Show Author Affiliations
Y. S. Ku, Industrial Technology Research Institute (Taiwan)
D. M. Shyu, Industrial Technology Research Institute (Taiwan)
W. T. Hsu, Industrial Technology Research Institute (Taiwan)
P. Y. Chang, Industrial Technology Research Institute (Taiwan)
Y. C. Chen, Industrial Technology Research Institute (Taiwan)
H. L. Pang, Industrial Technology Research Institute (Taiwan)

Published in SPIE Proceedings Vol. 8082:
Optical Measurement Systems for Industrial Inspection VII
Peter H. Lehmann; Wolfgang Osten; Kay Gastinger, Editor(s)

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