
Proceedings Paper
Partial reconfiguration of a peripheral in an FPGA-based SoC to analyse performance-area behaviourFormat | Member Price | Non-Member Price |
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Paper Abstract
Systems on Chip (SoC) are present in a wide range of applications. This diversity in addition with the quantity of critical
variables involved in their design process becomes it as a great challenging topic. FPGAs have consolidated as a
preferred device to develop and prototype SoCs, and consequently Partial Reconfiguration (PR) has gained importance
in this approach. Through PR it is possible to have a section of the FPGA operating, while other section is disabled and
partially reconfigured to provide new functionality. In this way hardware resources can be time-multiplexed and
therefore it is possible to reduce size, cost and power. In this case we focus on the implementation of a SoC, in an
FPGA-based board, with one of its peripherals being a reconfigurable partition (RP). Inside this RP different hardware
modules defined as reconfigurable modules (RM) can be configured. Thus, the system is suitable to have different
hardware configurations depending on the application needs and FPGA limitations, while the rest of the system
continues working. To this end a MicroBlaze soft-core processor is used in the system design and a Virtex-5 FPGA
board is utilized to its implementations. A remote sensing application is used to explore the capabilities of this approach.
Identifying the section(s) of the application suitable of being time-shared it is possible to define the RMs to place inside
the RP. Different configurations were carried out and measurements of area were taken. Preliminary results of the
performance-area utilisation are presented to validate the improvement in flexibility and resource usage.
Paper Details
Date Published: 3 May 2011
PDF: 9 pages
Proc. SPIE 8067, VLSI Circuits and Systems V, 806705 (3 May 2011); doi: 10.1117/12.887096
Published in SPIE Proceedings Vol. 8067:
VLSI Circuits and Systems V
Teresa Riesgo; Eduardo de la Torre-Arnanz, Editor(s)
PDF: 9 pages
Proc. SPIE 8067, VLSI Circuits and Systems V, 806705 (3 May 2011); doi: 10.1117/12.887096
Show Author Affiliations
Andres Cardona, Univ. Autònoma de Barcelona (Spain)
Yi Guo, Univ. Autònoma de Barcelona (Spain)
Institut de Ciències de l'Espai (Spain)
Yi Guo, Univ. Autònoma de Barcelona (Spain)
Institut de Ciències de l'Espai (Spain)
Published in SPIE Proceedings Vol. 8067:
VLSI Circuits and Systems V
Teresa Riesgo; Eduardo de la Torre-Arnanz, Editor(s)
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