Share Email Print

Proceedings Paper

Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs
Author(s): Juan Nuñez; María J. Avedillo; José M. Quintana
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. We compare RTD-CMOS and pure CMOS realizations of a network of logic gates which can be operated in a gate-level pipeline. Significant lower average power is obtained for RTD-CMOS implementations.

Paper Details

Date Published: 3 May 2011
PDF: 7 pages
Proc. SPIE 8067, VLSI Circuits and Systems V, 80670Z (3 May 2011); doi: 10.1117/12.886816
Show Author Affiliations
Juan Nuñez, IMSE-CNM-CSIC (Spain)
Univ. of Seville (Spain)
María J. Avedillo, IMSE-CNM-CSIC (Spain)
Univ. of Seville (Spain)
José M. Quintana, IMSE-CNM-CSIC (Spain)
Univ. of Seville (Spain)

Published in SPIE Proceedings Vol. 8067:
VLSI Circuits and Systems V
Teresa Riesgo; Eduardo de la Torre-Arnanz, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?