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Proceedings Paper

Analytical modeling of glitch propagation in nanometer ICs
Author(s): Xavier Gili; Salvador Barceló; Sebastià A. Bota; Jaume Segura
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Paper Abstract

We present a glitch propagation model that can be used to categorize the propagation likelihood of a given noise waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the glitch output characteristics given the input noise waveform for each gate in a 65- nm technology library. These noise transfer curves are fitted to known functions to have a simple analytical equation and compute the propagation. Comparison between simulations and model shows a good agreement.

Paper Details

Date Published: 3 May 2011
PDF: 6 pages
Proc. SPIE 8067, VLSI Circuits and Systems V, 80670Y (3 May 2011); doi: 10.1117/12.886448
Show Author Affiliations
Xavier Gili, Univ. de les Illes Balears (Spain)
Salvador Barceló, Univ. de les Illes Balears (Spain)
Sebastià A. Bota, Univ. de les Illes Balears (Spain)
Jaume Segura, Univ. de les Illes Balears (Spain)

Published in SPIE Proceedings Vol. 8067:
VLSI Circuits and Systems V
Teresa Riesgo; Eduardo de la Torre-Arnanz, Editor(s)

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