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Proceedings Paper

Accelerating sparse linear algebra using graphics processing units
Author(s): Kyle E. Spagnoli; John R. Humphrey; Daniel K. Price; Eric J. Kelmelis
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Paper Abstract

The modern graphics processing unit (GPU) found in many standard personal computers is a highly parallel math processor capable of over 1 TFLOPS of peak computational throughput at a cost similar to a high-end CPU with excellent FLOPS-to-watt ratio. High-level sparse linear algebra operations are computationally intense, often requiring large amounts of parallel operations and would seem a natural fit for the processing power of the GPU. Our work is on a GPU accelerated implementation of sparse linear algebra routines. We present results from both direct and iterative sparse system solvers. The GPU execution model featured by NVIDIA GPUs based on CUDA demands very strong parallelism, requiring between hundreds and thousands of simultaneous operations to achieve high performance. Some constructs from linear algebra map extremely well to the GPU and others map poorly. CPUs, on the other hand, do well at smaller order parallelism and perform acceptably during low-parallelism code segments. Our work addresses this via hybrid a processing model, in which the CPU and GPU work simultaneously to produce results. In many cases, this is accomplished by allowing each platform to do the work it performs most naturally. For example, the CPU is responsible for graph theory portion of the direct solvers while the GPU simultaneously performs the low level linear algebra routines.

Paper Details

Date Published: 20 May 2011
PDF: 9 pages
Proc. SPIE 8060, Modeling and Simulation for Defense Systems and Applications VI, 806004 (20 May 2011); doi: 10.1117/12.884169
Show Author Affiliations
Kyle E. Spagnoli, EM Photonics, Inc. (United States)
John R. Humphrey, EM Photonics, Inc. (United States)
Daniel K. Price, EM Photonics, Inc. (United States)
Eric J. Kelmelis, EM Photonics, Inc. (United States)

Published in SPIE Proceedings Vol. 8060:
Modeling and Simulation for Defense Systems and Applications VI
Eric J. Kelmelis, Editor(s)

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