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Proceedings Paper

Joint optimization of layout and litho for SRAM and logic towards the 20nm node using 193i
Author(s): Peter De Bisschop; Bart Laenens; Kazuya Iwase; Teruyoshi Yao; Mircea Dusa; Michael C. Smayling
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Paper Abstract

This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes, it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the layout-style - litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial wafer results).

Paper Details

Date Published: 22 March 2011
PDF: 18 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 79730B (22 March 2011); doi: 10.1117/12.881688
Show Author Affiliations
Peter De Bisschop, IMEC (Belgium)
Bart Laenens, IMEC (Belgium)
Kazuya Iwase, Sony Corp. (Belgium)
Teruyoshi Yao, Fujitsu Semiconductor Europe (Belgium)
Mircea Dusa, ASML (Belgium)
Michael C. Smayling, Tela Innovations, Inc. (United States)

Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

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