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Proceedings Paper

Custom source and mask optimization for 20nm SRAM and logic
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Paper Abstract

The 20nm generation for logic will be challenging for optical lithography, with a contacted gate pitch of ~82nm and a minimum metal pitch of ~64nm. A gridded design approach with lines and cuts has previously been shown to allow optimizing illuminator conditions for critical layers in logic designs.[1] The approach has shown good pattern fidelity and is expected to be scalable to the 7nm logic node. [2,3,4] A regular pattern for logic makes the optimization problem straightforward if only standard cells are used in a chip. However, modern SOC's include large amounts of SRAM memory as well. The proposed approach truly optimizes both, instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches. We consider a design with the logic and SRAMs unified from the beginning. In this case, critical layer orientations as well as pitches are matched and each of the layers optimized for both functional sets of patterns. The layout for a typical standard cell using Gridded Design rules is shown in Figure 1a. The Gate electrodes are oriented in the vertical direction, with Active regions running horizontally. Figure 1b shows a group of SRAM bit cells designed to be compatible with the logic cell. The Gate orientation and pitch are the same. Optimization results will be presented for the co-optimization of critical layers for the cells. The Source-Mask Optimization (SMO) method used can optimize the illumination source [5] and mask for multiple patterns to improve the 2-D image fidelity and process window while controlling the mask sensitivity. It can incorporate the design intentions that are implied by Gridded Design rules. SMO will be done to balance complexity of the source and the complexity of the mask (OPC & MBSRAFs). A flexible approach to the optimization will be introduced.

Paper Details

Date Published: 22 March 2011
PDF: 8 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 79731W (22 March 2011); doi: 10.1117/12.881662
Show Author Affiliations
Michael C. Smayling, Tela Innovations, Inc. (United States)
Tamer H. Coskun, Cadence Design Systems, Inc. (United States)
Vishnu Kamat, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

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