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Proceedings Paper

Investigation of processing performance and requirements for next generation lithography cluster tools
Author(s): M. Enomoto; T. Shimoaoki; K. Nafus; N. Nakashima; K. Tsutsumi; H. Marumoto; H. Kosugi; P. Derwin; R. Maas; C. Verspaget; J. Mallmann; R. Vangheluwe; I. Lamers; E. van der Heijden; S. Wang
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Paper Abstract

In this paper we summarize our investigations into processing capability on the CLEAN TRACKTM LITHIUS ProTM -i & TWINSCANTM NXT:1950i litho cluster. Process performance with regards to critical dimension (CD) uniformity and defectivity are investigated to confirm adherence to ITRS1 roadmaps specifications. Additionally, a study of wafer backside particle contamination is performed to understand the implications towards processing. As wafer stage chuck cleaning on the scanner will require considerable down time, this study is necessary to understand the requirements for manufacturability. Previous work from our collaboration succeeded in a processing improvement of over 80% in across wafer CD variation by implementing the newest post exposure bake (PEB) plate design2 and optimized developer process. With regards to defectivity, the use of the advanced defect reduction (ADR) process with an optimized bevel cut of the resist allowed the use of a high contact angle material process which is required for optimal immersion hood performance. In this work, further optimization of the process with consideration of the design concept of the TWINSCANTM NXT:1950i and hardware modifications on the CLEAN TRACKTM LITHIUS ProTM -i will be performed. From this investigation, it is expected to understand the process capability of 38nm CD uniformity using novel developer hardware. Additionally, the defectivity challenges for processing with higher scan speeds in combination with the hydrophobicity of the coating materials and edge cut strategy will be clarified. Initial evaluation results are analyzed to understand the correlation of various types and densities of contaminates on the backside of the wafer to the formation of wafer stage chuck focus spots (FS). Focus spots are a localized irregular focus and leveling height.

Paper Details

Date Published: 15 April 2011
PDF: 11 pages
Proc. SPIE 7972, Advances in Resist Materials and Processing Technology XXVIII, 79722X (15 April 2011); doi: 10.1117/12.879380
Show Author Affiliations
M. Enomoto, Tokyo Electron Kyushu Ltd. (Japan)
T. Shimoaoki, Tokyo Electron Kyushu Ltd. (Japan)
K. Nafus, Tokyo Electron Kyushu Ltd. (Japan)
N. Nakashima, Tokyo Electron Kyushu Ltd. (Japan)
K. Tsutsumi, Tokyo Electron Kyushu Ltd. (Japan)
H. Marumoto, Tokyo Electron Kyushu Ltd. (Japan)
H. Kosugi, Tokyo Electron Kyushu Ltd. (Japan)
P. Derwin, ASML Netherlands B.V. (Netherlands)
R. Maas, ASML Netherlands B.V. (Netherlands)
C. Verspaget, ASML Netherlands B.V. (Netherlands)
J. Mallmann, ASML Netherlands B.V. (Netherlands)
R. Vangheluwe, ASML Netherlands B.V. (Netherlands)
I. Lamers, ASML Netherlands B.V. (Netherlands)
E. van der Heijden, ASML Netherlands B.V. (Netherlands)
S. Wang, ASML Netherlands B.V. (Netherlands)

Published in SPIE Proceedings Vol. 7972:
Advances in Resist Materials and Processing Technology XXVIII
Robert D. Allen; Mark H. Somervell, Editor(s)

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