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Proceedings Paper

Using templates and connectors for layout pattern minimization in 20nm and below technology nodes
Author(s): Tejas K. Jhaveri; Andrzej J. Strojwas
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Paper Abstract

Layout pattern minimization has become a necessity at the 20nm technology node. Not only is it the only way to guarantee convergence for source mask optimization, having a well defined design space by limiting the total number of layout patterns, is the only way to ensure complete verification of design space during technology bring-up. In this paper we would reveal the details of PDF Solutions template and connector based layout design methodology that enables designers to achieve competitive layout density by limiting layout patterns. The use of this methodology enables a 25X pattern count reduction compared to the gridded logic layouts and is the only solution available that ensure pattern count saturation within a 40um x 40um random block of logic. Results on SMO compatibility have been highlighted by the collaborative work between ASML and PDF Solutions. In this paper we have discussed the development of a layout fabric developed for SMO and DPT compatibility, the definition of the base template and corresponding connector templates to provide the fabric constraints to designers and results highlighting the lithographic benefits of this approach. In effect, we have proposed a design solution that can provide a low-risk 20nm technology node enablement.

Paper Details

Date Published: 4 April 2011
PDF: 7 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797405 (4 April 2011); doi: 10.1117/12.879234
Show Author Affiliations
Tejas K. Jhaveri, PDF Solutions, Inc. (United States)
Andrzej J. Strojwas, PDF Solutions, Inc. (United States)

Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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