Share Email Print

Proceedings Paper

3D lithography modeling for ground rule development
Author(s): Chandra Sarma; Todd Bailey; Adam Lyons; Dongbing Shao
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The ability to incorporate the effect of patterned underlayers in a 3-dimensional physical resist model that truly mimics the process on real wafers could be used to formulate robust ground rules for design. We have shown as an example block level simulations, where the resist critical dimension is determined by the presence of STI (shallow trench isolation) and/or patterned gate level underneath & their relative spacing, as confirmed on wafer. We will demonstrate how the results of such study could be used for creating ground rules which are truly dependent on the interaction between the current layer resist & the patterned layers underneath. We have also developed a new way to visualize lithographic process variations in 3-D space that is useful for simulation analysis that can prove very helpful in ground rule development and process optimization. Such visualization capability in the dataprep flow to flag issues or dispose critical structures increases speed and efficiency in the mask tapeout process.

Paper Details

Date Published: 22 March 2011
PDF: 10 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 797315 (22 March 2011); doi: 10.1117/12.879213
Show Author Affiliations
Chandra Sarma, Infineon Technologies (United States)
Todd Bailey, IBM Microelectronics (United States)
Adam Lyons, IBM Microelectronics (United States)
Dongbing Shao, IBM Microelectronics (United States)

Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

© SPIE. Terms of Use
Back to Top